Semiconductor Device

• US 20110012132A1
• Filed: 02/06/2009
• Published: 01/20/2011
• Est. Priority Date: 02/06/2008
• Status: Abandoned Application

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Otsuka, Takukazu, Mitani, Shuhei
• Application Number:
  US12/866,528
• Publication Number:
  US 20110012132A1
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 1 which is stacked on a surface of the n⁺-type substrate 11 containing SiC; n⁺-type source regions 5 arranged away from each other in a surface layer of the epitaxial layer 1; a p-type well contact region 2 sandwiched by the source regions 5; a p-type well region 3 arranged in contact with surfaces of the source regions 5 and p-type well contact region 2 on the substrate 11 side; and p-type well extension regions 4 arranged to sandwich the source regions 5 and p-type well region 3. The impurity concentration of the p-type well region 3 has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer 1 toward the substrate 11 than the position of a peak concentration of the p-type well extension regions 4.

Claims

1. A semiconductor device comprising:

a substrate which contains silicon carbide and includes a first main electrode region;

a first conductivity-type epitaxial layer which is stacked on the a front surface of the substrate and is made of silicon carbide;

first conductivity-type second main electrode regions arranged away from each other in a surface layer of the epitaxial layer;

a second conductivity-type well contact region sandwiched by the second main electrode regions;

a second conductivity-type well region arranged in contact with surfaces of the second main electrode regions and the second conductivity-type well contact region on the substrate side;

second conductivity-type well extension regions arranged to sandwich the second main electrode regions and the second conductivity-type well region;

gate electrodes arranged on surfaces of the second conductivity-type well extension regions with gate insulating films interposed therebetween, each second conductivity-type well extension region being sandwiched by the corresponding one of the second main electrode regions and a surface exposed portion of the epitaxial layer;

a second main electrode arranged in contact with surfaces of the second main electrode regions and the second conductivity-type well contact region in a shared manner; and

a first main electrode arranged on a rear surface of the substrate opposite to the front surface, wherein

concentration of a second conductivity-type impurity contained in the second conductivity-type well region has a peak concentration at a deeper position than the position of a peak concentration of the second conductivity-type impurity contained in the second conductivity-type well extension regions in a depth direction from the surface of the epitaxial layer toward the substrate.

2. The semiconductor device according to claim 1, wherein

the first main electrode region is of a first conductivity type,

the first main electrode region is a drain region,

the second main electrode regions are a source region,

the first main electrode is a drain electrode, and

the second main electrode is a source electrode.

3. The semiconductor device according to claim 1, wherein

the first main electrode region is of a second conductivity type,

the first main electrode region is a collector region,

the second main electrode regions are an emitter region,

the first main electrode is a collector electrode, and

the second main electrode is an emitter electrode.

4. The semiconductor device according to claim 1, wherein

the concentration of the second conductivity-type impurity at the position of the peak concentration in the second conductivity-type well region is higher than concentration of the second conductivity-type impurity at the position of the peak concentration in each second conductivity-type well extension region.

5. The semiconductor device according to claim 1, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.

6. The semiconductor device according to claim 2, wherein

the concentration of the second conductivity-type impurity at the position of the peak concentration in the second conductivity-type well region is higher than concentration of the second conductivity-type impurity at the position of the peak concentration in each second conductivity-type well extension region.

7. The semiconductor device according to claim 3, wherein

the concentration of the second conductivity-type impurity at the position of the peak concentration in the second conductivity-type well region is higher than concentration of the second conductivity-type impurity at the position of the peak concentration in each second conductivity-type well extension region.

8. The semiconductor device according to claim 2, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.

9. The semiconductor device according to claim 3, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.

10. The semiconductor device according to claim 4, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.

11. The semiconductor device according to claim 6, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.

12. The semiconductor device according to claim 7, wherein

the depth of the surface of the second conductivity-type well region on the substrate side from the surface of the epitaxial layer is greater than that of the surface of each second conductivity-type well extension region on the substrate side.