Vertical Channel Transistor Structure and Manufacturing Method Thereof

• US 20110012192A1
• Filed: 09/28/2010
• Published: 01/20/2011
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Shih, Yen-Hao, Wu, Chia-Wei, Hsu, Tzu-Hsuan
• Granted Patent: US 9,246,015 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Claims

1. A vertical channel transistor structure, comprising:

a substrate;

a channel protruded from the substrate;

a cap layer deposited on the channel, wherein the cap layer and the channel substantially have the same width;

a charge trapping layer deposited on the cap layer and on two vertical surfaces of the channel;

a gate straddling on the charge trapping layer and positioned on the two vertical surfaces of the channel; and

a source and a drain respectively positioned on the two sides of the channel and opposing to the gate.

2. The vertical channel transistor structure according to claim 1, further comprising a thick silicon oxide (SiO) layer positioned on the substrate.

3. The vertical channel transistor structure according to claim 1, wherein the cap layer comprises a silicon dioxide (SiO₂) layer and a silicon nitride (SiN) layer, the SiN layer is positioned on the SiO₂ layer.

4. The vertical channel transistor structure according to claim 1, wherein the charge trapping layer is made from SiN or aluminum oxide (Al₂0₃).

5. The vertical channel transistor structure according to claim 4, further comprising a first SiO layer and a second SiO layer, wherein the first SiO layer is positioned between the charge trapping layer and the channel, and the second SiO layer is positioned between the charge trapping layer and the gate.

6. The vertical channel transistor structure according to claim 1, wherein the substrate is a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.

7. The vertical channel transistor structure according to claim 1, wherein the gate is made from N+ polysilicon, P+ polysilicon, or metal.

8. The vertical channel transistor structure according to claim 1, wherein the line width of the channel approximately ranges between 10 nm˜

60 nm.