EVALUATION OF AN UNDERCUT OF DEEP TRENCH STRUCTURES IN SOI WAFERS

• US 20110012236A1
• Filed: 01/19/2007
• Published: 01/20/2011
• Est. Priority Date: 01/20/2006
• Status: Abandoned Application

• Current Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Original Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Inventors: Hoelzer, Gisbert, Freywald, Karlheinz
• Application Number:
  US12/161,669
• Publication Number:
  US 20110012236A1
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A technique is provided which enables quantitative evaluation of an undercutting of deep trench structures in semiconductor wafers and, in particular, SOI wafers, by means of electrical or optical measuring. A specific control structure (100) having a defined ridge width is used which can be routinely measured in the course of the production process. The control structure comprises two adjacent trenches (5) each which are separated by a ridge having a defined ridge width. By undercutting (U) the adjacent trenches, the regions of undercutting of adjacent trenches may intersect each other starting from a specific minimum ridge width which results in a detachment of the ridge from the bottom making the ridge moveable. Mobility is determined by thermal deflection of the ridge. Arranging a plurality of control structures having various ridge widths enables determination of a quantitative amount of the undercutting.

Claims

1. A method for evaluating an undercutting of deep trench structures in a semiconductor wafer wherein a control structure (100, 100b) is created on the semiconductor wafer, which control structure is configured such that as a result of a trench etching of a silicon layer of the semiconductor wafer, a silicon ridge (4b) is provided having a defined width between two adjacent trenches, the ridge being undermined (U) when undercuts merge into each other, wherein:

said silicon ridge is heated after the trench etching, said undermined ridge (4b) thereby caused to move as compared to a non-undermined silicon ridge; and

said movement is registered and serves as a criterion of a ridge mobility.

2. The method according to claim 1, wherein said silicon ridge is heated electrically.

3. The method according to claim 1, wherein said movement is registered electrically.

4. The method according to claim 1, wherein said silicon ridge is heated by radiation.

5. The method according to claim 1, wherein said silicon ridge is heated electrically and said movement is registered optically.

6. The method according to claim 1, wherein said silicon ridge is deflected until it contacts a trench wall, whereby an electrical contact is made, said contact then being registered.

7. The method according to claim 1, wherein control structures having variously defined stepped ridge widths are disposed on a semiconductor wafer and the amount of undercutting is determined after trench etching on the basis of registration of ridge movement and knowledge of the respective defined ridge width.

8. The method according to claim 4, wherein said said silicon ridge is heated by laser radiation.

9. The method according to claim 1, wherein adjacent trenches forming said ridge are configured such that a preferred lateral direction for a deflection of said ridge is obtained upon heating of said ridge.

10. The method according to claim 1, wherein said semiconductor wafer has a SOI structure having a hidden insulating layer and a semiconductor layer formed thereon.

11. The method according to claim 10, wherein said trench structure is formed down to the hidden insulating layer.

31. The method according to claim 1, wherein said movement is for evaluating and assessing an amount of undercutting.

32. The method according to claim 1, wherein said movement is registered optically.

33. The method according to claim 2, wherein said movement is registered electrically.

12. A method for evaluating an undercutting of a deep trench structure in a substrate suitable for the production of a micro-structure component, comprising:

producing a silicon ridge having a ridge width between two adjacent trenches by trench etching of a silicon layer of the substrate;

generating a current flow in said silicon ridge; and

assessing the amount of undercutting of said silicon ridge occurring during trench etching in a deeper region of the adjacent trenches using the generated current flow and a material loss of said ridge determined by the amount of undercutting.

13. The method according to claim 12, wherein generating the current flow comprises imprinting a suitable current for determining conductivity of said silicon ridge.

14. The method according to claim 12, wherein the current flow is generated in a suitable level for heating said silicon ridge, whereby said undermined ridge is caused to move in a clearly recognizable manner as compared to a non-undermined ridge due to expansion, said movement is registered and serves as a criterion of ridge mobility for assessing the amount of undercutting.

15. An arrangement for evaluating an undercutting of a deep trench structure in a semiconductor wafer comprising:

a component area for receiving micro-structure components, said area being defined by a trench structure (5A) having a given trench width;

a first control structure (100) having a structure different from that of said micro-structure components and a silicon ridge formed by two adjacent trenches (5) having a certain width and being partially open between said adjacent trenches, wherein said silicon ridge is fixed at both ends thereof and comprises a contact surface for contacting by an external test probe.

17. The arrangement according to claim 15, wherein a further contact surface formed in a semiconductor layer is provided which is electrically insulated from the contact surfaces of said silicon ridge.

18. The arrangement according to claim 15, wherein said silicon ridge has a curvature in order to define a preferred lateral direction upon thermal expansion of said silicon ridge.

19. The arrangement according to claim 15, wherein one or more further control structures having a ridge are provided, wherein said ridge of said one or more further control structures is formed by adjacent trenches having a defined trench width and has a ridge width differing from that of said silicon ridge of said first control structure.

20. The arrangement according to claim 15, wherein said adjacent trenches forming said silicon ridge of said first control structure extend in such a way that said first control structure is fully enclosed.

21. The arrangement according to claim 20, wherein said adjacent trenches extend down to a hidden insulation layer.

16. (canceled)

22. An arrangement for evaluating an undercutting of a structure of deep trenches in a SOI wafer comprising:

a component area defined by trenches having a defined width;

a plurality of control structures located outside said component area, each control structure comprising one respective silicon ridge formed by adjacent trenches having a defined width, and wherein silicon ridge widths at a surface are provided with values graded in a defined manner so that said silicon ridges have various amounts of undercutting due to trench etching and thus various amounts of lateral mobility, wherein at least one contact surface for making contact with an external probe is provided in each control structure, said contact surface being connected with a respective silicon ridge.

23. The arrangement according to claim 22, wherein each silicon ridge has a curvature so that a preferred lateral direction is defined upon thermal expansion of said silicon ridges.

24. The arrangement according to claim 23, wherein said curvature has a radius of curvature being greater than a length of an associated silicon ridge.

25. (canceled)

26. An arrangement in the form of a control structure for evaluating an undercutting of a deep trench structure in a SOI wafer, configured such that a silicon ridge having a defined ridge width is formed between two adjacent trenches extending substantially in parallel with each other in a portion of said arrangement as a result of trench etching, said silicon ridge is undermined when undercuts merge into each other and regions are formed in two portions adjacent to the ends of said silicon ridge which are not completely undermined during etching;

wherein said trench comprises a closed trench, which encloses all three portions of said control structure;

wherein contact points are provided in non-undermined portions at ends of said silicon ridge and in an adjacent non-etched semiconductor area for electric heating of said silicon ridge and for measuring a deflection thereof due to heating.

27. The arrangement according to claim 26, wherein said silicon ridge has a curvature to be described by a specific radius of curvature in order to define an unambiguous direction of deflection of said silicon ridge upon heating.

28. The arrangement according to claim 26, wherein the arrangement is configured such that a number of ridges of various widths are provided.

29. A method for evaluating an undercutting of deep trench structures in SOI wafers using a control structure created on said SOI wafers, which control structure is configured such that a silicon ridge having a defined ridge width is formed between two adjacent trenches extending in parallel with each other as a result of trench etching, which silicon ridge is undermined when undercuts merge into each other, wherein said silicon ridge is heated after trench etching, whereby said undermined silicon ridge is caused to move in comparison to a non-undermined ridge, due to expansion, said movement being registered and serving as a criterion of mobility for evaluating an amount of undercutting.

30. The method according to claim 29, wherein said silicon ridge is heated electrically and said movement is registered electrically.