SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110012266A1
• Filed: 07/08/2010
• Published: 01/20/2011
• Est. Priority Date: 07/17/2009
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: HORIUCHI, Michio, Sakaguchi, Yuta, Matsuda, Yuichi, Tokutake, Yasue, Yamasaki, Tomoo
• Granted Patent: US 8,138,609 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0116 : Porous, e.g. foam
• CPC Class Codes: H05K 2201/09609 : Via grid, i.e. two-dimensional array of vias or holes in a single plane interposers H05K2201/10378
• CPC Class Codes: H05K 2201/09945 : Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0315 : Oxidising metal
• CPC Class Codes: H05K 2203/1142 : Conversion of conductive material into insulating material or into dissolvable compound
• CPC Class Codes: H05K 3/4605 : made from inorganic insulating material

Abstract

In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Claims

1. A semiconductor device comprising:

a substrate having a plurality of line conductors which penetrate the substrate from a top surface of the substrate to a bottom surface of the substrate;

a semiconductor chip secured in a semiconductor-chip accommodating hole of the substrate;

a first insulating layer formed on the top surface of the substrate and on a top surface of the semiconductor chip;

a first wiring layer formed on the first insulating layer, the first wiring layer in a first through hole of the first insulating layer being electrically connected to the semiconductor chip, and the first wiring layer in a second through hole of the first insulating layer being electrically connected to some of the plurality of line conductors exposed to the second through hole of the first insulating layer;

a second insulating layer formed on the bottom surface of the substrate and on a bottom surface of the semiconductor chip; and

a second wiring layer formed on the second insulating layer, the second wiring layer in a through hole of the second insulating layer being electrically connected to some of the plurality of line conductors exposed to the through hole of the second insulating layer.

2. The semiconductor device according to claim 1, wherein the plurality of line conductors are arranged so that a spacing between two adjacent line conductors of the plurality of line conductors is smaller than a diameter of each line conductor.

3. The semiconductor device according to claim 1, wherein the plurality of line conductors include an isolated line conductor which is electrically isolated from other line conductors.

4. The semiconductor device according to claim 1, wherein the plurality of line conductors include a first line conductor connected to a signal wiring line, and a second line conductor located in a peripheral area of the first line conductor, and the second line conductor is connected to a ground wiring line.

5. The semiconductor device according to claim 4, wherein an isolated line conductor which is electrically isolated from other line conductors is arranged between the first line conductor and the second line conductor.

6. The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are provided.

7. The semiconductor device according to claim 1, wherein the substrate includes a plurality of through holes formed therein and the plurality of through holes include a semiconductor chip accommodating hole for the semiconductor chip and a passive-component accommodating hole for a passive component.

8. The semiconductor device according to claim 1, wherein each of the plurality of line conductors has a diameter in a range of 30 nm-2000 nm.

9. A laminated type semiconductor device in which a plurality of the semiconductor devices according to claim 1 are laminated together.

10. A method of manufacturing a semiconductor device, comprising:

preparing a substrate including a plurality of line conductors which penetrate the substrate from a top surface of the substrate to a bottom surface of the substrate;

forming a semiconductor-chip accommodating hole in the substrate;

forming a first insulating layer on a top surface of the substrate to block an end of the semiconductor-chip accommodating hole;

securing a semiconductor chip in the semiconductor-chip accommodating hole so that a top surface of the semiconductor chip is in contact with the first insulating layer;

forming a first wiring layer on the first insulating layer, the first wiring layer in a first through hole of the first insulating layer being electrically connected to the semiconductor chip, and the first wiring layer in a second through hole of the first insulating layer being electrically connected to some of the plurality of line conductors exposed to the second through hole of the first insulating layer;

forming a second insulating layer on a bottom surface of the substrate to block the other end of the semiconductor-chip accommodating hole; and

forming a second wiring layer on the second insulating layer, the second wiring layer in a through hole of the second insulating layer being electrically connected to some of the plurality of line conductors exposed to the through hole of the second insulating layer.