APPARATUS AND METHOD FOR TESTING SENSE AMPLIFIER THRESHOLDS ON AN INTEGRATED CIRCUIT

• US 20110012643A1
• Filed: 07/15/2009
• Published: 01/20/2011
• Est. Priority Date: 07/15/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Klass, Edgardo F., Jain, Ashish R.
• Granted Patent: US 8,154,275 B2
• Time in Patent Office: Days
• US Class Current: 327/52
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage.

Claims

1. An integrated circuit comprising:

one or more sense amplifier modules, each including;

one or more sense amplifier circuits;

a voltage generator unit configured to selectably supply a differential voltage of a plurality of differential voltages to at least some of the one or more sense amplifier circuits;

wherein each sense amplifier circuit is configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal; and

detection logic coupled to each of the sense amplifier circuits and configured to detect an output value of each of the one or more sense amplifier circuits.

2. The integrated circuit as recited in claim 1, wherein the voltage generator unit is further configured to iteratively select a different differential voltage in response to a control input.

3. The integrated circuit as recited in claim 1, wherein the detection logic is further configured to capture the output value upon each change in differential voltage.

4. The integrated circuit as recited in claim 1, wherein the voltage generator unit comprises a voltage divider circuit having a plurality of output nodes and a multiplexer configured to select one of the output nodes as one of the differential voltages at a given time.

5. The integrated circuit as recited in claim 1, wherein the detection logic comprises one or more latch circuits, each configured to latch and output the output value of a corresponding one of the one or more sense amplifier circuits.

6. The integrated circuit as recited in claim 5, wherein the detection logic comprises one or more flip-flop circuits, each coupled to a corresponding one of the latch circuits, wherein each flip-flop circuit is configured to capture and output a digital value that corresponds to the output value.

7. The integrated circuit as recited in claim 6, wherein the one or more flip-flop circuits are coupled together in a scan chain such that an output of a first flip-flop is coupled to a scan data input of a next flip-flop and an output of the last flip-flop in the scan chain is coupled to a scan data output of the integrated circuit, and wherein in response to an assertion of a scan enable signal and a number of clock signal pulses, the captured digital values may be sequentially shifted out to the scan data output.

8. An integrated circuit comprising:

one or more sense amplifier circuits;

a voltage generator unit configured to selectably supply a differential voltage of a plurality of differential voltages to at least some of the one or more sense amplifier circuits;

wherein each sense amplifier circuit is configured to generate an output signal that is dependent upon the applied differential voltage in response to receiving an enable signal; and

detection logic coupled to each of the sense amplifier circuits and configured to detect an output value of each of the one or more sense amplifier circuits.

9. The integrated circuit as recited in claim 8, wherein the output value of each of the at least some of the sense amplifier circuits indicates whether a given sense amplifier circuit was able to detect a particular differential voltage.

10. The integrated circuit as recited in claim 8, wherein a transition in the output value of a given sense amplifier circuit corresponds to an operational threshold voltage differential for the given sense amplifier circuit.

11. The integrated circuit as recited in claim 8, wherein the voltage generator unit is further configured to iteratively select a different differential voltage in response to a control input.

12. The integrated circuit as recited in claim 8, wherein the detection logic is further configured to latch and output the output value of a corresponding one of the one or more sense amplifier circuits.

13. The integrated circuit as recited in claim 12, wherein the detection logic further comprises one or more flip-flop circuits, each configured to capture and output a digital value that corresponds to the output value of a corresponding one of the latch circuits in response to a transition of clock signal.

14. A sense amplifier module comprising:

a sense amplifier circuit configured to output an output value corresponding to a received differential input voltage;

a voltage generator unit configured to selectably apply a plurality of the differential input voltages, one at a time, to an input of the sense amp;

detection logic configured to detect whether an output of the sense amplifier indicates successful operation for each of the differential voltages.

15. The sense amplifier module as recited in claim 14, wherein the detection logic is configured to latch and output the output value of the sense amplifier circuit.

16. The sense amplifier module as recited in claim 15, wherein the detection logic further comprises one or more flip-flops, each configured to capture and output a digital value that corresponds to the output value of a corresponding one of the latch circuits in response to a transition of clock signal that is provided following each change in a voltage level of the second voltage supply.

20. The method as recited in claim 15, further comprising for each of the at least some sense amplifier circuits, the detection logic capturing the output value and outputting a corresponding digital value in response to a transition of clock signal.

17. A method comprising:

executing a sense amplifier test using a sense amplifier module including a plurality of sense amplifier circuits within an integrated circuit, wherein executing the sense amplifier test comprises;

a voltage generator unit selectably supplying a differential voltage of a plurality of differential voltages to at least some of the plurality of sense amplifier circuits;

wherein the at least some of the sense amplifier circuits generating an output signal that is dependent upon the applied differential voltage and in response to receiving an enable signal; and

detection logic detecting an output value of each of the plurality of sense amplifier circuits.

18. The method as recited in claim 17, further comprising the voltage generator unit iteratively selecting a different differential voltage in response to a control input.

19. The method as recited in claim 17, wherein iteratively selecting a different differential voltage includes a multiplexer selecting a different output node of a voltage divider network.