SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE CONNECTION

• US 20110012669A1
• Filed: 07/14/2010
• Published: 01/20/2011
• Est. Priority Date: 07/15/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: IO Semiconductor, Inc
• Inventors: Stuber, Michael A., Nygaard, Paul A., Molin, Stuart B.
• Granted Patent: US 8,232,597 B2
• Time in Patent Office: Days
• US Class Current: 327/530
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 : combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Claims

1. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being located above said electrically conductive layer, and partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body; and

a body contact physically connecting said electrically conductive layer and said body, being located in a first portion of said excavated insulator region;

wherein said electrically conductive layer couples said body contact to a contact in said active layer, said contact being located in a second portion of said excavated insulator region, said second portion being detached from said first portion.

2. The semiconductor-on-insulator device of claim 1, further comprising:

a circuit branch comprising said body contact and said contact;

wherein said circuit branch connects a source of said active device to said body of said active device.

3. The semiconductor-on-insulator device of claim 1, further comprising:

a circuit branch comprising said body contact and said contact;

wherein said circuit branch connects a gate of said active device to said body of said active device.

4. The semiconductor-on-insulator device of claim 1, further comprising:

a variable impedance circuit branch comprising said body contact and said contact;

wherein said variable impedance circuit branch is configured to have a high impedance when said active device is in an on state, and said variable impedance circuit branch is configured to have a low impedance when said active device is not in said on state.

5. The semiconductor-on-insulator device of claim 4, said variable impedance circuit branch further comprising:

a gate region of said active device;

wherein said variable impedance circuit branch latches said body to said gate voltage when said active device is in an off state.

6. The semiconductor-on-insulator device of claim 5, wherein:

said body contact is ohmic;

said contact is directly below a diode formed in said active layer; and

said diode is reversed biased when said active device is in an on state.

7. The semiconductor-on-insulator device of claim 5, wherein said body contact is a hot-carrier diode junction.

8. The semiconductor-on-insulator device of claim 7, further comprising a handle wafer above said active layer.

9. The semiconductor-on-insulator device of claim 8, further comprising:

a landing pad formed above said body contact;

wherein said landing pad is comprised of a wider region of said body.

10. A method of removing unwanted accumulated majority-type carriers from the channel of a semiconductor-on-insulator active device comprising the steps of:

conducting said unwanted accumulated majority-type carriers from said channel to a body contact of said active device, said body contact physically connecting an electrically conductive layer and a body of said active device; and

conducting said unwanted accumulated majority-type carriers through a circuit branch in said electrically conductive layer, said electrically conductive layer being located below an insulator layer and partially vertically coextensive with said insulator layer in an excavated insulator region;

wherein said circuit branch couples said body contact to a contact, said body contact being located in a first portion of said excavated insulator region, and said contact being located in a second detached portion of said excavated insulator region.

11. The method from claim 10, further comprising the step of:

increasing an impedance of said circuit branch when said active device is in an on state; and

decreasing an impedance of said circuit branch when said active device is not in said on state.

12. The method from claim 11, further comprising the step of latching said body contact to a gate of said active device through a diode connection.

13. The method from claim 12, wherein said diode is a hot-carrier diode formed by an interface of said electrically conductive layer and said body.

14. A method of fabricating an integrated circuit, the method comprising the steps of:

forming an active device in an active layer of a semiconductor-on-insulator wafer;

removing a substrate material from a substrate layer disposed on a back side of said semiconductor-on-insulator wafer;

removing an insulator material from a back side of said semiconductor-on-insulator wafer to form an excavated insulator region; and

depositing an electrically conductive layer on said excavated insulator region;

wherein said depositing puts said electrically conductive layer in physical contact with a body of an active device in a first portion of said excavated insulator region, and couples said body to a contact, said contact being in a second detached portion of said excavated insulator region.

15. The method of fabricating an integrated circuit from claim 14, further comprising the step of forming a circuit branch from said contact to a source of said active device.

16. The method of fabricating an integrated circuit from claim 14, wherein said depositing forms a segment of a variable impedance circuit branch configured to have a high impedance when said active device is in an on state, and have a low impedance when said active device is not in said on state.

17. The method of fabricating an integrated circuit from claim 14, further comprising the step of forming a gate region of said active device and a second segment of a variable impedance circuit branch from said gate to said contact.

18. The method of fabricating an integrated circuit from claim 14, further comprising the step of forming a diode in said active layer directly above said contact, said diode configured to be reversed biased when said active device is in an on state.

19. The method of fabricating an integrated circuit from claim 18, wherein said depositing forms a hot-carrier diode junction between said active layer and said electrically conductive layer.

20. The method of fabricating an integrated circuit from claim 19, wherein said forming said active device in said active layer further comprises forming a landing pad above said body contact, said landing pad being comprised of a wider region of said body.

21. A semiconductor-on-insulator structure comprising:

an electrically conductive layer;

an insulator layer being at least partially vertically coextensive with said electrically conductive layer in an excavated insulator region;

an active layer being located above said insulator layer, and comprising an active device with a body; and

a body contact physically connecting said electrically conductive layer and said body;

wherein said electrically conductive layer couples said body contact to a contact in said active layer.