ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL PANEL, LIQUID CRYSTAL DISPLAY DEVICE, LIQUID CRYSTAL DISPLAY UNIT, AND TELEVISION RECEIVER

• US 20110012815A1
• Filed: 10/30/2008
• Published: 01/20/2011
• Est. Priority Date: 03/31/2008
• Status: Abandoned Application

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tsubata, Toshihide
• Application Number:
  US12/922,756
• Publication Number:
  US 20110012815A1
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134354 the sub-pixels being capacitively coupled
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2203/30 Gray scale
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2320/028 by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

An active matrix substrate includes: scan signal lines 16x; data signal lines 15x; and switching elements (12a, 12b), the active matrix substrate further including, in each pixel region (100): a pixel electrode (17a) connected to a corresponding one of the data signal lines (15x) via a corresponding one of the switching elements (12a); a pixel electrode (17b) connected to the corresponding one of the data signal lines (15x) via the corresponding one of the switching elements (12b); and a pixel electrode (17c) connected to the pixel electrode (17a) via a capacitance (Cac), the pixel (100) being intersected by a corresponding one of the scan signal lines (16x) so as to be divided into two parts, the pixel electrode (17a) being provided in one of the two parts, the pixel electrode (17b) being provided in the other one of the two parts. Therefore, it is possible to provide an active matrix substrate of a capacitively-coupled pixel-dividing type, which is advantageous in flexibility in layout of each pixel electrode.

Claims

1. An active matrix substrate comprising:

scan signal lines;

switching elements each connected to a corresponding one of the scan signal lines;

data signal lines;

the active matrix substrate further comprising, in each pixel region;

a first pixel electrode connected to a corresponding one of the data signal lines via a corresponding one of the switching elements;

a second pixel electrode connected to the corresponding one of the data signal lines via a corresponding one of the switching elements; and

a third pixel electrode connected to the first pixel electrode via a capacitance,

the pixel region being intersected by a corresponding one of the scan signal lines so as to be divided into two parts,

the first pixel electrode being provided in one of the two parts,

the second pixel electrode being provided in the other one of the two parts.

2. The active matrix substrate as set forth in claim 1, wherein:

in planar view, each of the first pixel electrode and the second pixel electrode are provided adjacent to the corresponding one of the scan signal lines.

3. The active matrix substrate as set forth in claim 1, wherein:

the first pixel electrode and the third pixel electrode are provided in the one of the two parts.

4. The active matrix substrate as set forth in claim 1, further comprising:

first retention capacitance lines each overlapping a part of edges of corresponding third pixel electrodes with each other,

each of the first retention capacitance lines having first extending portions branching therefrom,

each of the first extending portions, in planar view, extending so that the first extending portion and the other part of edges of a corresponding one of the third pixel electrodes overlap each other, or, alternatively, the first extending portion extending around the other part of edges of the corresponding one of the third pixel electrodes and then merging into the first retention capacitance line again.

5. The active matrix substrate as set forth in claim 4, wherein:

the first extending portions and the first pixel electrodes overlap each other, respectively.

6. The active matrix substrate as set forth in claim 4, wherein:

the first extending portions are provided one per pixel region and are connected to their neighboring first extending portion in a column direction.

7. The active matrix substrate as set forth in claim 4, wherein:

the first retention capacitance lines are provided in such a manner that pixel regions in pair which are adjacent to each other share one first retention capacitance line.

8. The active matrix substrate as set forth in claim 3, further comprising:

first retention capacitance lines each overlapping a part of edges of corresponding third pixel electrodes with each other;

first sub-lines each of which forms retention capacitances in combination with corresponding first pixel electrodes; and

first conducting electrodes connected between the first retention capacitance line and the first sub-line, the first conducting electrodes being provided two per each pixel region in such a manner that a first sub-line and two first conducting electrodes corresponding to one pixel region are extended so that a combination of the first sub-line and the two first conducting electrodes, and the other part of edges of a corresponding one of the third pixel electrodes overlap each other, or, alternatively, that the combination of the first sub-line and the two first conducting electrodes is extended around the other part of edges of the corresponding one of the third pixel electrodes.

9. The active matrix substrate as set forth in claim 4, further comprising:

an interlayer insulating film provided below each of the first pixel electrode, the second pixel electrode, and the third pixel electrode,

the interlayer insulating film being less in thickness in at least (i) a part of a region where the third pixel electrode and the first retention capacitance line overlap each other, and (ii) a part of a region where the third pixel electrode and the first extending portion overlap each other.

10. The active matrix substrate as set forth in claim 9, wherein:

the interlayer insulating film includes an inorganic insulating film and an organic insulating film which is greater in thickness than the inorganic insulating film; and

the organic insulating film is absent in at least (i) the part of the region where the third pixel electrode and the first retention capacitance line overlap each other, and (ii) the part of the region where the third pixel electrode and the first extending portion overlap each other.

11. The active matrix substrate as set forth in claim 3, further comprising:

first retention capacitance lines each overlapping a part of edges of corresponding third pixel electrodes with each other; and

first shield electrodes each connected to a corresponding one of the first retention capacitance lines via a contact hole,

the first shield electrodes and the third pixel electrodes being provided in the same layer,

the first shield electrode, in planar view, extending around the other part of edges of a corresponding one of the third pixel electrodes.

12. The active matrix substrate as set forth in claim 11, further comprising:

an interlayer insulating film provided below each of the first pixel electrode, the second pixel electrode, and the third pixel electrode,

the interlayer insulating film including an inorganic insulating film and an organic insulating film which is greater in thickness than the inorganic insulating film.

13. The active matrix substrate as set forth in claim 1, further comprising, in each pixel region:

a first coupling capacitance electrode electrically connected to the first pixel electrode,

the first coupling capacitance electrode and the third pixel electrode overlapping each other via an interlayer insulating film which is provided below each of the first pixel electrode, the second pixel electrode, and the third pixel electrode.

14. The active matrix substrate as set forth in claim 13, wherein:

the switching element includes a first transistor;

the first pixel electrode is connected to, via a contact hole, a lead line led out of a conducting terminal of the first transistor; and

the lead line and the first coupling capacitance electrode are connected to each other in the same layer.

15-39. -39. (canceled)

40. An active matrix substrate comprising:

scan signal lines;

data signal lines;

first transistors each connected to both of a corresponding one of the scan signal lines and a corresponding one of the data signal lines; and

second transistors each connected to both of the corresponding one of the scan signal lines and the corresponding one of the data signal lines,

the active matrix substrate further comprising, in each pixel region;

a first pixel electrode connected to a corresponding one of the first transistors;

a second pixel electrode connected to a corresponding one of the second transistors; and

a third pixel electrode connected to the first pixel electrode via a capacitance,

the first pixel electrode and the second pixel electrode facing each other via a gap therebetween,

the pixel region being intersected by a corresponding one of the scan signal lines so that the corresponding one of the scan signal lines and the gap overlap each other.

41-49. -49. (canceled)