TFT. SHIFT REGISTER, SCAN SIGNAL LINE DRIVING CIRCUIT, DISPLAY DEVICE, AND TFT TRIMMING METHOD

• US 20110012880A1
• Filed: 01/27/2009
• Published: 01/20/2011
• Est. Priority Date: 06/12/2008
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kataoka, Yoshiharu, Kitagawa, Hideki, Imai, Hajime, Kikuchi, Tetsuo, Tanaka, Shinya
• Granted Patent: US 8,946,719 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 28/86 having horizontal extensions

Abstract

In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.

Claims

1. A TFT comprising:

a first capacitor formed so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween;

a second capacitor formed so as to have a region where a third capacitor electrode and a fourth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween;

a first lead-out line led out from the first capacitor electrode in a planar direction;

a second lead-out line led out from a gate electrode in a planar direction;

a third lead-out line out from the third capacitor electrode in a planar direction;

a fourth lead-out line led out from the fourth capacitor electrode in a planar direction;

a first interconnection intersecting the second lead-out line and the fourth lead-out line when viewed in the thickness direction; and

a second interconnection intersecting the first lead-out line and the third lead-out line when viewed in the thickness direction,

the second capacitor electrode and the gate electrode being connected to each other via the second lead-out line,

the third capacitor electrode and the source electrode not being connected to each other,

the fourth capacitor electrode and the gate electrode not being connected to each other.

3. The TFT according to claim 1, wherein

the first capacitor electrode, the third capacitor electrode, the first lead-out line, the third lead-out line, and the first interconnection are formed from source metal, and

the second capacitor electrode, the fourth capacitor electrode, the second lead-out line, the fourth lead-out line, and the second interconnection are formed from gate metal.

4. The TFT according to claim 1, wherein

each of the first dielectric layer and the second dielectric layer is a gate dielectric layer.

19. The TFT according to claim 1, wherein

the TFT is manufactured with use of amorphous silicon.

20. The TFT according to claim 1, wherein

the TFT is manufactured with use of microcrystalline silicon.

21. A shift register including a plurality of stages composed of transistors, wherein

at least one of the transistors is a TFT according to claim 1.

22. A scanning signal line drive circuit including a shift register according to claim 21, wherein

the shift register is used to generate a scan signal for a display device.

23. The scan signal line driving circuit according to claim 22, wherein

the TFT is an output transistor that outputs the scan signal.

24. A display device, comprising a scan signal line driving circuit according to claim 22.

25. The display device according to claim 24, wherein

the scan signal line driving circuit is formed on a display panel so as to be monolithically integrated with a display region.

26. A display device, comprising a display panel in which a TFT according to claim 1 is formed.

27. A method for trimming a TFT according to claim 1,

the method, comprising:

causing separation between the second capacitor electrode and the gate electrode by fusing the second lead-out line;

causing the first lead-out line and the third lead-out line to be connected to the second interconnection by welding; and

causing the second lead-out line and the fourth lead-out line to be connected to the first interconnection by welding.

2. A TFT comprising:

a first capacitor formed so that a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween;

a second capacitor formed so that a third capacitor electrode and a fourth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween;

a first lead-out line led out from the first capacitor electrode in a planar direction;

a second lead-out line led out from a gate electrode in a planar direction;

a third lead-out line led out from the third capacitor electrode in a planar direction;

a fourth lead-out line led out from the fourth capacitor electrode in a planar direction;

a first interconnection intersecting the second lead-out line and the fourth lead-out line when viewed in the thickness direction; and

a second interconnection intersecting the first lead-out line and the third lead-out line when viewed in the thickness direction,

the second capacitor electrode and the gate electrode not being connected to each other,

the first lead-out line and the third lead-out line being connected to the second interconnection, whereby the third capacitor electrode and the source electrode are connected to each other,

the second lead-out line and the fourth lead-out line being connected to the first interconnection, whereby the fourth capacitor electrode and the gate electrode are connected to each other.

5. A TFT comprising:

a lead-out line connected to a source electrode; and

a capacitor formed so as to have a region where a plurality of first capacitor electrodes and a second capacitor electrode connected to a gate electrode are arranged to be stacked in a thickness direction and mutually opposed across a dielectric layer therebetween, the plurality of first capacitor electrodes being led out from the lead-out line so as to be branched off from the lead-out line in a planar direction.

6. The TFT according to claim 5,

each of the first capacitor electrodes has:

a pairing portion forming an opposing pair with the second electrode which is in the region of the capacitor; and

a non-pairing portion with the second electrode such that the non-pairing portion extends from the lead-out line and leads to the pairing portion.

7. The TFT according to claim 6, wherein

a cutout is provided in the first capacitor electrode at a boundary between the non-pairing portion and the pairing portion and/or provided in the lead-out line at a place where the first capacitor electrode is branched off from the lead-out line.

8. The TFT according to claim 5, wherein

the first capacitor electrodes and the lead-out line are formed from source metal, and

the second capacitor electrode is formed from gate metal.

9. The TFT according to claim 5, wherein

the dielectric layer is a gate dielectric layer.

28. A method for trimming a TFT according to claim 5, the method, comprising:

causing disconnection of at least one of the first capacitor electrodes from the lead-out line by fusing.

10. A TFT comprising:

a first capacitor formed;

so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; and

so as to have a region where the first capacitor electrode and a third capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrode and the third capacitor electrode and a coupling between the first capacitor electrode and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode;

a second capacitor formed;

so as to have a region where a fourth capacitor electrode and a fifth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a third dielectric layer therebetween; and

so as to have a region where the fourth capacitor electrode and a sixth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a fourth dielectric layer therebetween with a coupling between the fourth capacitor electrode and the sixth capacitor electrode and a coupling between the fourth capacitor electrode and the fifth capacitor electrode formed over mutually opposite faces of the fourth capacitor electrode;

a first lead-out line led out from the first capacitor electrode in a planar direction;

a second lead-out line led out from the second capacitor electrode in a planar direction;

a gate lead-out line led out from a gate electrode in a planar direction;

a third lead-out line led out from the third capacitor electrode in a planar direction;

a fourth lead-out line led out from the fourth capacitor electrode in a planar direction;

a fifth lead-out line led out from the fifth capacitor electrode in a planar direction;

a first interconnection intersecting the gate lead-out line and the fifth lead-out line when viewed in the thickness direction; and

a second interconnection intersecting the first lead-out line and the fourth lead-out line when viewed in the thickness direction,

the third capacitor electrode and the gate electrode being connected to each other via the third lead-out line,

the sixth capacitor electrode being connected to the fifth lead-out line,

the second capacitor electrode and the gate electrode being connected to each other via the second lead-out line,

the gate lead-out line and the fifth lead-out line not being connected to the first interconnection,

the first lead-out line and the fourth lead-out line not being connected to the second interconnection.

12. The TFT according to claim 10, wherein

the first capacitor electrode, the fourth capacitor electrode, the first lead-out line, the fourth lead-out line, and the first interconnection are formed from source metal,

the second capacitor electrode, the fifth capacitor electrode, the second lead-out line, the fifth lead-out line, the gate lead-out line, and the second interconnection are formed from gate metal, and

the third capacitor electrode, the sixth capacitor electrode, and the third lead-out line are formed from transparent electrodes.

13. The TFT according to claim 10, wherein

each of the first dielectric layer and the third dielectric layer is a gate dielectric layer, and

each of the second dielectric layer and the fourth dielectric layer is a passivation layer.

29. A method for trimming a TFT according to claim 10,

the method, comprising:

causing separation between the third capacitor electrode and the gate electrode by fusing the third lead-out line;

causing the sixth capacitor electrode to be connected to the fifth lead-out line by welding;

causing separation between the second capacitor electrode and the gate electrode by fusing the second lead-out line;

causing the gate lead-out line and the fifth lead-out line to be connected to the first interconnection by welding; and

causing the first lead-out line and the fourth lead-out line to be connected to the second interconnection by welding.

11. A TFT comprising:

a first capacitor formed;

so as to have a region where a first capacitor electrode connected to a source electrode and a second capacitor electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween; and

so as to have a region where the first capacitor electrode and a third capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrode and the third capacitor electrode and a coupling between the first capacitor electrode and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode;

a second capacitor formed;

so as to have a region where a fourth capacitor electrode and a fifth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a third dielectric layer therebetween; and

so as to have a region where the fourth capacitor electrode and a sixth capacitor electrode are arranged to be stacked in the thickness direction and mutually opposed across a fourth dielectric layer therebetween with a coupling between the fourth capacitor electrode and the sixth capacitor electrode and a coupling between the fourth capacitor electrode and the fifth capacitor electrode formed over mutually opposite faces of the fourth capacitor electrode;

a first lead-out line led out from the first capacitor electrode in a planar direction;

a second lead-out line led out from the second capacitor electrode in a planar direction;

a gate lead-out line led out from a gate electrode in a planar direction;

a third lead-out line led out from the third capacitor electrode in a planar direction;

a fourth lead-out line led out from the fourth capacitor electrode in a planar direction;

a fifth lead-out line led out from the fifth capacitor electrode in a planar direction;

a first interconnection intersecting the gate lead-out line and the fifth lead-out line when viewed in the thickness direction; and

a second interconnection intersecting the first lead-out line and the fourth lead-out line when viewed in the thickness direction,

the third capacitor electrode and the gate electrode not being connected to each other,

the sixth capacitor electrode being connected to the fifth lead-out line,

the second capacitor electrode and the gate electrode not being connected to each other,

the gate lead-out line and the fifth lead-out line being connected to the first interconnection, whereby the fifth capacitor electrode and the sixth electrode are connected to the gate electrode,

the first lead-out line and the fourth lead-out line being connected to the second interconnection, whereby the fourth capacitor electrode and the source electrode are connected to each other.

14. A TFT comprising:

a lead-out line connected to a source electrode; and

a capacitor formed;

so as to have a region where a plurality of first capacitor electrodes and a second capacitor electrode connected to a gate electrode are arranged to be stacked in a thickness direction and mutually opposed across a first dielectric layer therebetween, the plurality of first capacitor electrodes being led out from the lead-out line so as to be branched off from the lead-out line in a planar direction; and

so as to have a region where the first capacitor electrodes and a third capacitor electrode connected to the gate electrode are arranged to be stacked in the thickness direction and mutually opposed across a second dielectric layer therebetween with a coupling between the first capacitor electrodes and the third capacitor electrode and a coupling between the first capacitor electrodes and the second capacitor electrode formed over mutually opposite faces of the first capacitor electrode.

15. The TFT according to claim 14,

each of the first capacitor electrodes has:

a pairing portion forming an opposing pair with either of the second and third capacitor electrodes closer to the lead-out line which electrodes are in the region of the capacitor; and

a non-pairing portion with the second and third electrodes such that the non-pairing portion extends from the lead-out line and leads to the pairing portion.

16. The TFT according to claim 15, wherein

a cutout is provided in the first capacitor electrode at a boundary between the non-pairing portion and the pairing portion and/or provided in the lead-out line at a place where the first capacitor electrode is branched off from the lead-out line.

17. The TFT according to claim 14, wherein

the first capacitor electrode and the lead-out line are formed from source metal,

the second capacitor electrode is formed from gate metal, and

the third capacitor electrode is formed from a transparent electrode.

18. The TFT according to claim 14, wherein

the first dielectric layer is a gate dielectric layer, and

the second dielectric layer is a passivation layer.