LIQUID CRYSTAL DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND LIQUID CRYSTAL DISPLAY APPARATUS USING THE SAME

• US 20110012941A1
• Filed: 09/28/2010
• Published: 01/20/2011
• Est. Priority Date: 09/23/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Yeon Ju, SHIN, Kyoung Ju, Chang, Hak Sun, Do, Hee Wook, Yoo, Seung Hoo, Kim, Hyun Wuk
• Granted Patent: US 8,207,923 B2
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2320/0673 for control of gamma adjustment, e.g. selecting another gamma curve
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

The disclosure describes a liquid crystal display panel including a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels has first and second gray scale regions which are split up and down and have different areas, first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to first and second gray scale regions so that first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven.

Claims

1. A liquid crystal display panel comprising:

a plurality of sub-pixels, wherein each sub-pixel includes a first gray scale region to which a first data signal is supplied according to a first gamma curve, a second gray scale region to which a second data signal is supplied according to a second gamma curve, and a third gray scale region electronically connected to the second gray scale region;

a first thin film transistor for driving the first gray scale region;

a second thin film transistor for driving the second and third gray scale regions;

a data line connected to the first and second thin film transistors, for supplying the first and second data signals;

a first gate line for driving the first thin film transistor; and

a second gate line for driving the second thin film transistor.

2. The liquid crystal display panel of claim 1, wherein the first gray scale region connected to the first thin film transistor is arranged in an upper part of the first gate line, and the second and third gray scale regions connected to the second thin film transistor are arranged in a lower part of the first gate line or any one of the second and third gray scale regions is arranged in the upper part.

3. The liquid crystal display panel of claim 2, wherein the second and third gray scale regions are arranged in the lower part in one sub-pixel, and the second and third gray scale regions are respectively arranged in the upper and lower parts in sub-pixels adjacent to both sides of the one sub-pixel.

4. The liquid crystal display panel of claim 3, wherein the areas of the second and third gray scale regions is one and half times to three times the area of the first gray scale regions.

5. The liquid crystal display panel of claim 1, wherein the first, second and third gray scale regions have a zigzag structure in which both sides of each of the first, second and third gray scale regions are bent on the basis of a horizontal axis to have a symmetrical tilt angle.

6. The liquid crystal display panel of claim 5, further comprising a storage line overlapped with a boundary between the gray scale regions which are adjacent to each other up and down, wherein contact holes for connecting the thin film transistors to the gray scale regions are overlapped with the storage line.