MULTI-CHIP PACKAGE STRUCTURE SUITABLE FOR MULTI-PROCESSOR SYSTEM HAVING MEMORY LINK ARCHITECTURE

• US 20110013353A1
• Filed: 03/03/2010
• Published: 01/20/2011
• Est. Priority Date: 07/14/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Bo-Il, Kwon, Jin-Hyoung
• Application Number:
  US12/717,027
• Publication Number:
  US 20110013353A1
• Time in Patent Office: Days
• US Class Current: 361/679.31
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A multi-chip package structure can include a first package that includes a first circuit board that includes a lower surface including a first circuit pattern thereon and an upper surface, that is opposite the lower surface, and includes an upper pad layer thereon. The multi-chip package structure can further include at least one processor chip that is mounted on the lower surface of the first circuit board. A second package can be mounted on the first package and can include a second circuit board including an upper surface that includes a second circuit pattern thereon and a lower surface, which is opposite the upper surface, which can includes a lower pad layer thereon that is electrically connected to the upper pad layer of the first circuit board. At least one memory chip can be laminated and molded on the upper surface of the second package.

Claims

1. A multi-chip package structure comprising:

a first package including

a first circuit board including a lower surface including a first circuit pattern thereon and an upper surface, opposite the lower surface, including an upper pad layer thereon, and

at least one processor chip mounted on the lower surface of the first circuit board, and

a second package, mounted on the first package, including

a second circuit board including an upper surface including a second circuit pattern thereon and a lower surface, opposite the upper surface, including a lower pad layer thereon electrically connected to the upper pad layer of the first circuit board, and

at least one memory chip laminated and molded on the upper surface of the second package.

2. The multi-chip package structure of claim 1, wherein the upper pad layer and the lower pad layer are connected to each other by respective land grid array pads.

3. The multi-chip package structure of claim 2, wherein the at least one processor chip is mounted on the lower surface of the first circuit board and is surrounded by contact pads on the lower surface of the first circuit board.

4. The multi-chip package structure of claim 3, wherein the at least one processor chip includes a MODEM chip and an application chip.

5. The multi-chip package structure of claim 4, wherein the at least one memory chip includes a OneNAND™

, a OneDRAM™

, and a multi-bank DRAM each having a laminated structure.

6. A multi-chip package structure comprising:

a first package including

a first circuit board having a lower surface including circuit patterns formed separately and an upper surface, opposite the lower surface, including an upper pad layer thereon and

processor chips mounted on the lower surface of the first circuit board to be connected to the circuit patterns, and

routing lines electrically connecting the processor chips; and

a second package including

a second circuit board including an upper surface including a circuit pattern and a lower surface, opposite the upper surface, including a lower pad layer electrically connected to the upper pad layer of the first package, and

at least one memory chip laminated and molded on the upper surface of the second package.

7. The multi-chip package structure of claim 6, wherein the upper pad layer and the lower pad layer are connected to each other by land grid array contact.

8. The multi-chip package structure of claim 7, wherein the processor chips are mounted on the lower surface of the first circuit board such that each of the processor chips is surrounded by contact pads on the lower surface of the first circuit board.

9. The multi-chip package structure of claim 6, wherein the routing lines are in or on the second circuit board.

10. The multi-chip package structure of claim 9, wherein the at least one memory chip includes a NAND flash memory, a multi-port semiconductor memory, and a multi-bank DRAM each having a laminated structure.

11. A multi-chip package structure comprising:

a first package including a first circuit board including a lower surface having a circuit pattern thereon and an upper surface having an upper pad layer thereon, and at least one first processor chip mounted on the lower surface of the first circuit board;

a second package including a second circuit board including a lower surface having a circuit pattern thereon and an upper surface including an upper pad layer thereon, and at least one second processor chip mounted on the lower surface of the second circuit board; and

a third package including

a third circuit board including an upper surface including a circuit pattern and a lower surface including a lower pad layer electrically connected to the upper pad layers of the first and second packages,

at least one memory chip laminated and molded on the upper surface of the third circuit board, and

routing lines electrically connecting the at least one first processor chip and the at least one second processor chip.