INVERTER TOPOLOGIES USABLE WITH REACTIVE POWER

• US 20110013438A1
• Filed: 07/20/2009
• Published: 01/20/2011
• Est. Priority Date: 07/20/2009
• Status: Active Grant

• Current Assignee: Vincotech Holdings SARL (Mitsubishi Electric Corporation)
• Original Assignee: Vincotech Holdings SARL (Mitsubishi Electric Corporation)
• Inventors: Frisch, Michael, Temesi, Ernö
• Granted Patent: US 8,582,331 B2
• Time in Patent Office: Days
• US Class Current: 363/131
• CPC Class Codes: H02J 2300/24 of photovoltaic origin
• CPC Class Codes: H02J 3/381 Dispersed generators
• CPC Class Codes: H02M 1/0085 Partially controlled bridges
• CPC Class Codes: H02M 7/48 using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: Y02E 10/56 Power conversion systems, e.g. maximum power point trackers

Abstract

The present invention generally relates to power electronic switching circuits and in particular to inverter modules employing two or more controlled switches that can be used with reactive loads. An inverter circuit is provided which comprises first and second input terminals for being connected to a DC power source; first and second output terminals for outputting an AC voltage; at least one metal oxide semiconductor field effect transistor, MOSFET, having a parasitic body diode. The inverter circuit further comprises at least one disabling element for disabling said body diode. This may result in an improved efficiency of the inverter circuit in combination with a reactive power capability. Further, a semiconductor switching device is disclosed, comprising at least one metal oxide semiconductor field effect transistor, MOSFET, and at least one insulated gate bipolar transistor, IGBT, wherein said MOSFET and said IGBT are connected in parallel.

Claims

1. Inverter circuit comprising:

first and second input terminals for being connected to a DC power source;

first and second output terminals for outputting an AC voltage;

at least one metal oxide semiconductor field effect transistor, MOSFET, having a parasitic body diode,

wherein said inverter circuit further comprises at least one disabling element for disabling said body diode.

2. Inverter circuit of claim 1, wherein said disabling element comprises at least one bypass diode for providing an alternative conduction path for a load current.

3. Inverter circuit of claim 2, wherein said bypass diode comprises a silicon carbide Schottky diode.

4. Inverter circuit of claim 2, wherein as a protection element a suppressor diode connected with a high voltage FRED is provided which protects the IGBT from reverse current when the parasitic capacity of the MOSFET is charged at switch-off.

5. Inverter circuit of claim 2, wherein as a protection element a capacitor paralleled with a resistor is provided.

6. Inverter circuit of claim 1, wherein said disabling element comprises an inductor for decoupling the MOSFET from a load.

7. Inverter circuit of claim 3, comprising four MOSFET which are connected to each other to form an H-bridge configuration, wherein a first inductor is provided between a source terminal of a fourth MOSFET and said first output terminal, a second inductor is provided between a drain terminal of a first MOSFET and said second output terminal, a third inductor is provided between a drain terminal of a second MOSFET and said first output terminal, and a fourth inductor is provided between a source terminal of a third MOSFET and said second output terminal.

8. Inverter circuit of claim 7, further comprising a bypass diode at the drain terminal of each MOSFET for providing an alternative conduction path for a reactive load current.

9. Inverter circuit of claim 7, wherein the first and third inductor are wound in the same direction and are arranged on a common coil.

10. Inverter circuit of claim 7, wherein the second and fourth inductor are wound in the same direction and are arranged on a common coil.

11. Neutral point clamped, NPC;

inverter circuit comprising;

a first input terminal for being connected to a DC voltage of a first polarity, and a second input terminal for being connected to a DC voltage of a polarity opposite to said first polarity;

an input neutral point terminal for being connected to a ground potential;

an output terminal for outputting an AC voltage;

at least one metal oxide semiconductor field effect transistor, MOSFET, having a parasitic body diode,

wherein said inverter circuit further comprises a disabling element for disabling said body diode.

12. NPC inverter circuit of claim 11, wherein said disabling element comprises at least one first bypass diode arranged between said first input electrode and said output terminal and at least one second bypass diode arranged between said second input electrode and said output terminal.

13. NPC inverter circuit of claim 11, further comprising at least one insulated gate bipolar transistor, IGBT, being connected to form a half-bridge with the at least one MOSFET.

14. NPC inverter circuit of claim 13, further comprising at least one suppressor diode which is coupled between the collector terminal and the emitter terminal of said at least one IGBT.

15. NPC inverter circuit of claim 11, wherein said disabling element comprises at least one inductor for inductively decoupling said output terminal.

16. NPC inverter circuit of claim 11, further comprising at least one insulated gate bipolar transistor, which is connected in parallel to the drain-source-path of said MOSFET.

17. Semiconductor switching device, comprising at least one metal oxide semiconductor field effect transistor, MOSFET, having a drain terminal and a source terminal, and at least one insulated gate bipolar transistor, IGBT, having a collector terminal and an emitter terminal, wherein said MOSFET and said IGBT are connected in parallel by coupling the collector terminal of the IGBT to the drain terminal of the MOSFET, and by coupling the emitter terminal of the IGBT to the source terminal of the MOSFET.

18. Neutral point clamped, NPC;

inverter circuit comprising;

a first input terminal for being connected to a DC voltage of a first polarity, and a second input terminal for being connected to a DC voltage of a polarity opposite to said first polarity;

an input neutral point terminal for being connected to a ground potential;

an output terminal for outputting an AC voltage;

wherein between said first input terminal and said output terminal a first semiconductor switching device is coupled, and wherein between said second input terminal and said output terminal a second semiconductor switching device is coupled,

said first and second semiconductor switching device comprising at least one metal oxide semiconductor field effect transistor, MOSFET, having a drain terminal and a source terminal, and at least one insulated gate bipolar transistor, IGBT, having a collector terminal and an emitter terminal, wherein said MOSFET and said IGBT are connected in parallel by coupling the collector terminal of the IGBT to the drain terminal of the MOSFET, and by coupling the emitter terminal of the IGBT to the source terminal of the MOSFET.

19. NPC inverter circuit of claim 18, further comprising two IGBT coupled between said input neutral point terminal and said output terminal.

20. NPC inverter circuit of claim 18, wherein said IGBT are coupled in series in opposite direction.

21. NPC inverter circuit of claim 18, wherein said IGBT are coupled in parallel in opposite direction.

22. NPC inverter circuit of claim 19, further comprising at least one inductor provided at the output terminal.