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NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE

  • US 20110013455A1
  • Filed: 09/10/2010
  • Published: 01/20/2011
  • Est. Priority Date: 11/27/2006
  • Status: Active Grant
First Claim
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1. A memory bank comprising:

  • a memory array having memory cells connected to bitlines and wordlines;

    a page buffer for latching data of the bitlines during a read operation, and for coupling the latched data to a predetermined number of datalines in parallel; and

    ,a sequential coupler for sequentially coupling each of the predetermined number of datalines to a bidirectional serial data line.

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