NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE

• US 20110013455A1
• Filed: 09/10/2010
• Published: 01/20/2011
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: KIM, Jin-Ki
• Granted Patent: US 8,289,805 B2
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1048 : Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Claims

1. A memory bank comprising:

a memory array having memory cells connected to bitlines and wordlines;

a page buffer for latching data of the bitlines during a read operation, and for coupling the latched data to a predetermined number of datalines in parallel; and

,

a sequential coupler for sequentially coupling each of the predetermined number of datalines to a bidirectional serial data line.

2. The memory bank of claim 1, wherein the sequential coupler includes a parallel/serial data converter having terminals coupled to each of the predetermined number of datalines, the parallel/serial data converter being controllable to sequentially couple each of the terminals to the bidirectional serial data line.

3. The memory bank of claim 1, wherein the sequential coupler includes a first parallel/serial data converter having first terminals coupled to each of the predetermined number of datalines, the first parallel/serial data converter being controllable for sequentially coupling each of the first terminals to a first local bidirectional serial data line,

a second parallel/serial data converter having second terminals coupled to each of the predetermined number of second datalines, the second parallel/serial data converter being controllable for sequentially coupling each of the second terminals to a second local bidirectional serial data line,

a data path selector for selectively coupling one of the first local bidirectional serial data line and the second local bidirectional serial data line to a global bidirectional serial data line.

4. The memory bank of claim 2, further including a counter responsive to a clock signal for controlling the first parallel/serial data converter and the second parallel/serial data converter.

5. The memory bank of claim 4 wherein the data path selector is controlled by a most significant bit of the counter not used by first parallel/serial data converter and the second parallel/serial data converter.

6. A memory bank comprising:

a first memory sector having memory cells connected to first bitlines and first wordlines, the first bitlines being arranged as m segments where m is an integer value greater than 0;

a second memory sector having memory cells connected to second bitlines and second wordlines, the second bitlines being arranged as m segments;

a page buffer for selectively coupling one of the first bitlines and the second bitlines of each of the m segments to a predetermined number of datalines.

7. The memory bank of claim 6, wherein a read operation is executed by

activating a wordline of one of the first wordlines in the first memory sector and the second wordlines in the second memory sector in response to a row address, at least two memory cells being coupled to the first bitlines when the wordline is one of the first wordlines, and at least two memory cells being coupled to the second bitlines when the wordline is one of the second wordlines,

selectively coupling one bitline of the first bitlines and the second bitlines to a common bitline in response to a column address,

sensing the common bitline with the page buffer, and

providing data corresponding to the sensed common bitline onto one of the predetermined number of datalines.

8. A page buffer for a memory bank comprising:

a first self-decoding page buffer stage for sensing data from a first set of common bitlines, and for providing sensed data corresponding to each of the common bitlines of the first set of common bitlines on corresponding data lines in response to an active column select bit latched in a clock signal state; and

,

a second self-decoding page buffer stage for sensing data from a second set of common bitlines, and for providing sensed data corresponding to each of the common bitlines of the second set of common bitlines on the corresponding data lines in response to the active column select bit latched in a subsequent clock signal state.

9. The page buffer of claim 8, wherein a self-decoding operation is executed by

latching the active column select bit in the first self-decoding page buffer stage in response to an opposite clock signal state,

providing the sensed data from the first self-decoding page buffer stage and passing the active column select bit in response to the clock signal state,

latching the active column select bit in the second self-decoding page buffer stage in response to a subsequent opposite clock signal state, and

providing the sensed data from the second self-decoding page buffer stage in response to the subsequent clock signal state.

10. A system comprising:

a memory controller for providing access data; and

a serial interconnection of a plurality of memory devices, each of the memory devices including;

a controller for receiving the access command and an address contained in access data, for executing an operation corresponding to the access command;

a memory bank for executing the operation in accordance with the access command to access data stored in a memory location addressed by the address; and

a serial data path for coupling the data in serial format between the memory bank and an input/output interface.