MEMORY DEVICES SUPPORTING SIMULTANEOUS PROGRAMMING OF MULTIPLE CELLS AND PROGRAMMING METHODS THEREOF
First Claim
1. A method of programming a memory device comprising an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines, the method comprising:
- boosting potentials of the vertical channels;
selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data; and
applying a program voltage to a selected word plate to thereby program a plurality of memory cells.
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Abstract
Some embodiments of the present invention provide methods of programming memory devices that include an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines. In some method embodiments, potentials of the vertical channels are boosted, followed by selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data. A program voltage is subsequently applied to a selected word plate to thereby program a plurality of cells.
73 Citations
46 Claims
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1. A method of programming a memory device comprising an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines, the method comprising:
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boosting potentials of the vertical channels; selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data; and applying a program voltage to a selected word plate to thereby program a plurality of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A three-dimensional memory device comprising:
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a memory cell array where a plurality of wordline planes are stacked; a write and read circuit configured to simultaneously program memory cells of at least two pages included in a selected wordline plane; and a control circuit configured to control a program operation of the write and read circuit. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for programming a three-dimensional memory device, comprising:
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performing channel boosting by applying a first pass voltage to a plurality of wordline planes; loading program data to memory cells of at least two pages disposed at a selected one of the wordline planes; and simultaneously programming the memory cells to which the program data is loaded. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A memory system comprising:
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a three-dimensional memory device; and a memory controller configured to control operations of the three-dimensional memory device in response to the request from a host, wherein the three-dimensional memory device includes a memory cell array where a plurality of wordline planes are stacked, a write and read circuit configured to simultaneously program memory cells of at least two pages included in a selected wordline plane, and a control circuit configured to control a program operation of the write and read circuit.
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Specification