SUB-BEAM FORMING RECEIVER CIRCUITRY FOR ULTRASOUND SYSTEM

• US 20110013488A1
• Filed: 07/15/2009
• Published: 01/20/2011
• Est. Priority Date: 07/15/2009
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Zhang, Zhenyong, Yousefi, Masood, Ma, Wei, Bahai, Ahmad, Wang, Shougang
• Granted Patent: US 8,248,885 B2
• Time in Patent Office: Days
• US Class Current: 367/135
• CPC Class Codes: G01S 15/8927 using simultaneously or sequentially two or more subarrays or subapertures
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G10K 11/346 using phase variation

Abstract

Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.

Claims

1. An apparatus including multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system, comprising:

input signal delay circuitry responsive to one or more clock signals and each one of a plurality of incoming digital data signals by providing a respective plurality of delayed digital data signals;

signal selection circuitry coupled to said input signal delay circuitry and responsive to a first plurality of control data by selecting among each said respective plurality of delayed digital data signals to provide a plurality of selected delayed digital data signals;

output signal delay circuitry coupled to said signal selection circuitry and responsive to a second plurality of control data by delaying each of said plurality of selected delayed digital data signals to provide a plurality of further delayed digital data signals; and

signal combining circuitry coupled to said output signal delay circuitry and responsive to said plurality of further delayed digital data signals by combining said plurality of further delayed digital data signals to provide a corresponding output data signal.

2. The apparatus of claim 1, wherein said input signal delay circuitry comprises:

filter circuitry responsive to each one of a plurality of incoming digital data signals by providing a respective plurality of filtered digital data signals;

sampling circuitry coupled to said filter circuitry and responsive to each said respective plurality of filtered digital data signals by providing a respective plurality of sampled digital data signals; and

data storage circuitry coupled to said sampling circuitry and responsive to each said respective plurality of sampled digital data signals by providing said respective plurality of delayed digital data signals.

3. The apparatus of claim 1, wherein said signal selection circuitry comprises signal routing circuitry.

4. The apparatus of claim 1, wherein said output signal delay circuitry comprises data storage circuitry.

5. The apparatus of claim 1, wherein said signal combining circuitry comprises signal summing circuitry.

6. The apparatus of claim 1, wherein:

said input signal delay circuitry provides said respective plurality of delayed digital data signals in accordance with a first delay;

said output signal delay circuitry provides said plurality of further delayed digital data signals in accordance with a second delay; and

said first delay is less than said second delay.

7. The apparatus of claim 1, wherein said input signal delay circuitry comprises:

first filter circuitry responsive to a first one of said one or more clock signals and said each one of said plurality of incoming digital data signals by providing a respective plurality of first filtered digital data signals;

first delay circuitry coupled to said first filter circuitry and responsive to each said respective plurality of first filtered digital data signals by providing a respective plurality of first delayed digital data signals;

first sampling circuitry coupled to said first delay circuitry and responsive to each said respective plurality of first delayed digital data signals by providing a respective plurality of first sampled digital data signals;

second filter circuitry coupled to said first sampling circuitry and responsive a second one of said one or more clock signals and to each said respective plurality of first sampled digital data signals by providing a respective plurality of second filtered digital data signals;

second delay circuitry coupled to said second filter circuitry and responsive to each said respective plurality of second filtered digital data signals by providing a respective plurality of second delayed digital data signals; and

second sampling circuitry coupled to said second delay circuitry and responsive to each said respective plurality of second delayed digital data signals by providing a respective plurality of second sampled digital data signals.

8. The apparatus of claim 7, wherein:

said first one of said one or more clock signals has a first frequency;

said second one of said one or more clock signals has a second frequency; and

said second frequency is one-half of said first frequency.

9. The apparatus of claim 7, wherein said input signal delay circuitry further comprises:

third filter circuitry coupled to said first sampling circuitry and responsive a third one of said one or more clock signals and to each said respective plurality of second sampled digital data signals by providing a respective plurality of third filtered digital data signals;

third delay circuitry coupled to said third filter circuitry and responsive to each said respective plurality of third filtered digital data signals by providing a respective plurality of third delayed digital data signals; and

third sampling circuitry coupled to said third delay circuitry and responsive to each said respective plurality of third delayed digital data signals by providing a respective plurality of third sampled digital data signals.

10. The apparatus of claim 9, wherein:

said first one of said one or more clock signals has a first frequency;

said second one of said one or more clock signals has a second frequency;

said third one of said one or more clock signals has a third frequency;

said second frequency is one-half of said first frequency; and

said third frequency is one-fourth of said first frequency.

11. An apparatus including multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system, comprising:

input signal delay means for receiving one or more clock signals and each one of a plurality of incoming digital data signals and in response thereto providing a respective plurality of delayed digital data signals;

signal selector means for receiving a first plurality of control data and in response thereto selecting among each said respective plurality of delayed digital data signals to provide a plurality of selected delayed digital data signals;

output signal delay means for receiving a second plurality of control data and in response thereto delaying each of said plurality of selected delayed digital data signals to provide a plurality of further delayed digital data signals; and

signal combiner means for combining said plurality of further delayed digital data signals to provide a corresponding output data signal.