Method of Forming Low Resistance Gate for Power MOSFET Applications

• US 20110014763A1
• Filed: 09/27/2010
• Published: 01/20/2011
• Est. Priority Date: 02/10/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Ho, Ihsiu, Sreekantham, Sreevatsa, Naylor, James Kent, Session, Fred
• Granted Patent: US 8,592,277 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Abstract

A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.

Claims

1-51. -51. (canceled)

52. A method of forming a trench gate field effect transistor, comprising:

forming a trench in a silicon region;

forming a dielectric layer lining the trench sidewalls and bottom;

forming a recessed polysilicon layer in the trench;

forming a highly conductive cap layer over and in contact with the recessed polysilicon layer; and

performing rapid thermal processing to cause the recessed polysilicon layer and the highly conductive cap layer to react.

53. The method of claim 52 further comprising:

forming a protective layer over the highly conductive layer, the protective layer serving to prevent dopants in its underlying layers from diffusing out.

54. The method of claim 52 further comprising:

prior to forming a recessed polysilicon layer;

forming a polysilicon layer in a bottom half of the trench;

forming a highly conductive material over and in contact with the polysilicon layer in the bottom half of the trench, wherein the step of performing rapid thermal processing causes the polysilicon layer in the bottom half of the trench and the highly conductive material to react.

55. The method of claim 52 wherein the highly conductive cap layer comprises one or more of tungsten, tantalum and Molly.

56. The method of claim 52 wherein the step of forming a highly conductive layer comprises depositing the conductive layer using directional deposition.

57. The method of claim 56 further comprising:

prior to performing rapid thermal processing, completely removing the vertically extending portions of the highly conductive layer while horizontally extending portions of the conductive layer remain including a horizontally extending portion over the recessed polysilicon layer;

forming a protective layer recessed in the trench over the horizontally portion of the highly conductive layer extending over the recessed polysilicon layer; and

etching the conductive layer to remove unprotected portions of the conductive layer extending over surfaces of the silicon region.

58. The method of claim 57 wherein the completely removing step comprises isotropically etching the highly conductive layer.

59. The method of claim 57 wherein the protective layer comprises one of polysilicon and BPSG.

60. The method of claim 52 wherein the highly conductive cap layer comprises a salicidable material.

61. The method of claim 52 wherein the rapid thermal processing causes a portion of the highly conductive cap layer directly in contact with the recessed polysilicon layer to react with the recessed polysilicon, the method further comprising:

removing un-reacted portions of the highly conductive cap layer using selective etch.

62. The method of claim 61 further comprising:

after removing the un-reacted portions, performing another rapid thermal processing to cause the reacted portion of the highly conductive cap layer to go through a phase transformation thereby reducing its resistance.

63. The method of claim 52 wherein the silicon region comprises a substrate of a first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the silicon region;

forming a well region of a second conductivity type in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trench.

64. A method of forming a shielded gate field effect transistor, comprising:

lining lower sidewalls and bottom of the trench with shield dielectric;

filling a lower portion of the trench with a shield electrode;

forming an inter-electrode dielectric over the shield electrode;

forming a dielectric layer lining upper trench sidewalls and extending over surfaces of the silicon region adjacent the trench;

forming a recessed polysilicon layer in the trench over the inter-electrode dielectric;

forming a highly conductive cap layer over and in contact with the recessed polysilicon layer; and

performing rapid thermal processing to cause the recessed polysilicon layer and the highly conductive cap layer to react.

65. The method of claim 64 further comprising:

forming a protective layer over the highly conductive layer, the protective layer serving to prevent dopants in its underlying layers from diffusing out.

66. The method of claim 64 wherein the highly conductive cap layer comprises one or more of tungsten, tantalum and Molly.

67. The method of claim 64 wherein the step of forming a highly conductive layer comprises depositing the conductive layer using directional deposition.

68. The method of claim 67 further comprising:

prior to performing rapid thermal processing, completely removing the vertically extending portions of the highly conductive layer while horizontally extending portions of the conductive layer remain including a horizontally extending portion over the recessed polysilicon layer;

forming a protective layer recessed in the trench over the horizontally portion of the highly conductive layer extending over the recessed polysilicon layer; and

etching the conductive layer to remove unprotected portions of the conductive layer extending over surfaces of the silicon region.

69. The method of claim 68 wherein the completely removing step comprises isotropically etching the highly conductive layer.

70. The method of claim 68 wherein the protective layer comprises one of polysilicon and BPSG.

71. The method of claim 64 wherein the highly conductive cap layer comprises a salicidable material.

72. The method of claim 64 wherein the rapid thermal processing causes a portion of the highly conductive cap layer directly in contact with the recessed polysilicon layer to react with the recessed polysilicon, the method further comprising:

removing un-reacted portions of the highly conductive cap layer using selective etch.

73. The method of claim 72 further comprising:

after removing the un-reacted portions, performing another rapid thermal processing to cause the reacted portion of the highly conductive cap layer to go through a phase transformation thereby reducing its resistance.

74. The method of claim 64 wherein the silicon region comprises a substrate of a first conductivity type, the method further comprising:

forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the silicon region;

forming a well region of a second conductivity type in the epitaxial layer; and

forming source regions of the first conductivity type in the well region adjacent the trench.

75-140. -140. (canceled)