METHOD OF FORMING A DUAL-TRENCH FIELD EFFECT TRANSISTOR

• US 20110014764A1
• Filed: 09/29/2010
• Published: 01/20/2011
• Est. Priority Date: 01/30/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce D.
• Granted Patent: US 8,829,641 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a field effect transistor includes forming a well region in a semiconductor region of a first conductivity type. The well region may be of a second conductivity type and have an upper surface and a lower surface. The method also includes forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region, and forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below the plurality of gate trenches. The plurality of stripe trenches may be laterally spaced from the plurality of gate trenches. The method also includes at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type. The semiconductor material of the second conductivity type may form a PN junction with a portion of the semiconductor region.

Claims

1. A method of forming a field effect transistor comprising:

forming a well region in a semiconductor region of a first conductivity type, the well region being of a second conductivity type and having an upper surface and a lower surface;

forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region;

forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below that of the plurality of gate trenches, the plurality of stripe trenches being laterally spaced from one or more of the plurality of gate trenches; and

at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.

2. The method of claim 1 wherein the plurality of stripe trenches extend into the semiconductor region parallel to a current flow through the semiconductor region when the field effect transistor is in an on state.

3. The method of claim 1 wherein the plurality of stripe trenches are completely filled with the semiconductor material of the second conductivity type using selective epitaxial growth.

4. The method of claim 1 wherein the semiconductor material of the second conductivity type lines the sidewalls of the plurality of stripe trenches, the method further comprising:

forming a dielectric material within the plurality of stripe trenches such that each stripe trench becomes substantially completely filled with the combination of the semiconductor material of the second conductivity type and the dielectric material.

5. The method of claim 1 wherein the plurality of stripe trenches are formed after forming the plurality of gate trenches and the well region.

6. The method of claim 1 wherein the semiconductor region is an epitaxial layer of the first conductivity type in which the well region is formed, the epitaxial layer having a thickness defined by the spacing between an upper surface and a lower surface of the epitaxial layer, wherein the plurality of stripe trenches extend into the epitaxial layer and terminate at a depth between one-half the thickness of the epitaxial layer and the lower surface of the epitaxial layer.

7. The method of claim 1 wherein the semiconductor region has a thickness defined by the vertical distance between an upper surface and a lower surface of the semiconductor region, the plurality of stripe trenches terminating within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.

8. The method of claim 3 further comprising forming source regions in the well region.

9. The method of claim 8 wherein the semiconductor region comprises an epitaxial layer and a substrate both of the first conductivity type, the substrate forming a drain contact region, the method further comprising:

forming the epitaxial layer over the substrate, the well region being formed in the epitaxial layer, and the plurality of stripe trenches and gate trenches extending into and terminating within the epitaxial layer.