Architectures for an Implantable Medical Device System

• US 20110015705A1
• Filed: 09/16/2010
• Published: 01/20/2011
• Est. Priority Date: 06/25/2007
• Status: Abandoned Application

• Current Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Original Assignee: Boston Scientific Neuromodulation Corporation (Boston Scientific Corporation)
• Inventors: Nimmagadda, Kiran, Feldman, Emanuel, Marnfeldt, Goran N., Shi, Jess W., Aghassisn, Daniel, Griffith, Paul J., Parramon, Jordi
• Application Number:
  US12/883,797
• Publication Number:
  US 20110015705A1
• Time in Patent Office: Days
• US Class Current: 607/66
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/0551 Spinal or peripheral nerve electrodes
• CPC Class Codes: A61N 1/0553 Paddle shaped electrodes, e.g. for laminotomy
• CPC Class Codes: A61N 1/36071 Pain
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components

Abstract

An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.

Claims

1. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient'"'"'s tissue, comprising:

a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of the plurality of first electrodes;

a second integrated circuit comprising a second stimulation circuitry block for controlling stimulation of the plurality of first electrodes; and

a bus in communication with both the first and second integrated circuits, wherein communications on the bus occurs in accordance with a bus protocol.

2. The device of claim 1, wherein the first and second stimulation circuitry blocks respectively comprise first and second digital-to-analog converter circuitry for respectively providing stimulation to the plurality of first and second electrodes.

3. The device of claim 1, further comprising an electrode array coupled to the first and second electrodes.

4. The device of claim 3, wherein the electrode array comprises a plurality of electrode leads.

5. The device of claim 1, further comprising a controller in communication with the bus, wherein the controller controls the first and second integrated circuits via the bus.

6. The device of claim 5, wherein the controller comprises an integrated circuit separate from the first and second integrated circuits.

7. The device of claim 5, wherein the controller resides on one of the first or second integrated circuits.

8. The device of claim 1, wherein the first and second integrated circuits are similarly constructed.

9. The device of claim 1, wherein the protocol comprises an address-before-data protocol.

10. The device of claim 9, wherein the bus comprises a plurality of signals for carrying in parallel both data and addresses, wherein the data and addresses are time-multiplexed on the plurality of signals.

11. The device of claim 10, wherein the bus comprises a write enable signal line and a read enable signal line.

12. The device of claim 11, wherein the bus comprises an address latch enable signal line for latching a read or write address.

13. The device of claim 1, wherein each of the first and second integrated circuits further comprises a plurality of functional blocks each coupled to the bus.

14. The device of claim 1, wherein the first and second stimulation circuitry blocks and the plurality of functional blocks on the first and second integrated circuits each couple to the bus using bus interface circuitry.

15. The device of claim 1, wherein the first integrated circuit comprises a master for controlling the second integrated circuit as a slave.

16. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient'"'"'s tissue, comprising:

a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of the plurality of first electrodes;

a second integrated circuit comprising a second stimulation circuitry block for controlling stimulation of the plurality of first electrodes, wherein the first and second integrated circuits are similarly constructed; and

a controller for controlling the first and second integrated circuits.

17. The device of claim 16, wherein the first and second stimulation circuitry blocks respectively comprise first and second digital-to-analog converter circuitry for respectively providing stimulation to the plurality of first and second electrodes.

18. The device of claim 16, further comprising an electrode array coupled to the first and second electrodes.

19. The device of claim 18, wherein the electrode array comprises a plurality of electrode leads.

20. The device of claim 16, wherein the controller comprises an integrated circuit separate from the first and second integrated circuits.

21. The device of claim 16, wherein the controller resides on one of the first or second integrated circuits.

22. The device of claim 16, wherein the first and second integrated circuits and the controller are each coupled to a communication bus, wherein communication on the bus occurs in accordance with a bus protocol.

23. The device of claim 22, wherein the protocol comprises an address-before-data protocol.

24. The device of claim 16, wherein each of the first and second integrated circuits further comprises a plurality of functional blocks each coupled to the bus.

25. The device of claim 24, wherein the first and second stimulation circuitry blocks and the plurality of functional blocks on the first and second integrated circuits each couple to a communication bus using bus interface circuitry.