APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION

• US 20110016236A1
• Filed: 09/28/2010
• Published: 01/20/2011
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: OH, HakJune, PYEON, Hong Beom, KIM, Jin-Ki, SUMI, Shuji
• Granted Patent: US 8,195,839 B2
• Time in Patent Office: Days
• US Class Current: 710/9
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. A memory controller can recognize the total number of one DT, in response to the ID received from the last device. In a case of a “don'"'"'t care” DT is provided to the interconnected devices, IDs are sequentially generated and the total number of the interconnected devices is recognized, regardless of the differences in DTs of the devices.

Claims

1. A system comprising:

a signal processor capable of outputting a serial input signal and receiving a serial output signal; and

a serial interconnection configuration of first to N-th devices of mixed type, N being an integer greater than one, each of the devices having a serial input connection and a serial output connection, each of the devices being capable of determining a device type (DT) and providing a combination of the DT and a device identifier (ID),

the serial input connection of one of the devices being coupled to the signal processor or the serial output connection of a previous device,

the serial output connection of the one of the devices being coupled to the serial input connection of a next device or the signal processor,

the serial input signal provided to the serial input connection of the first device from the signal processor being propagated through the N devices with or without being altered, the propagated serial input signal being outputted from the serial output connection of the N-th device as the serial output signal received by the signal processor.