SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE

• US 20110016250A1
• Filed: 04/15/2010
• Published: 01/20/2011
• Est. Priority Date: 07/16/2009
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Bhakta, Jayesh R.
• Granted Patent: US 8,516,185 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Claims

1. A memory module comprising:

at least one printed circuit board;

a plurality of memory devices mechanically coupled to the at least one printed circuit board;

a control circuit mechanically coupled to the at least one printed circuit board, the control circuit configurable to receive control signals from a system memory controller and to transmit module control signals to the plurality of memory devices; and

a plurality of data transmission circuits mechanically coupled to the at least one printed circuit board and distributed at corresponding positions relative to the at least one printed circuit board, the plurality of data transmission circuits configurable to be operatively coupled to the system memory controller and configurable to receive module control signals from the control circuit,

wherein at least one first data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices, at least one second data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices,

wherein the at least one first data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one first data transmission circuit, and the at least one second data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one second data transmission circuit.

2. The memory module of claim 1, wherein the at least one first data transmission circuit comprises a byte-wise buffer.

3. The memory module of claim 2, wherein the at least one second data transmission circuit comprises a byte-wise buffer.

4. The memory module of claim 1, wherein the at least one first data transmission circuit has the same bit width as does each of the at least two memory devices to which the at least one first data transmission circuit is operatively coupled.

5. The memory module of claim 4, wherein the at least one second data transmission circuit has the same bit width as does each of the at least two memory devices to which the at least one second data transmission circuit is operatively coupled.

6. The memory module of claim 1, wherein the at least one first data transmission circuit has a first bit width and each of the at least two memory devices to which the at least one first data transmission circuit is operatively coupled has a second bit width which is less than the first bit width.

7. The memory module of claim 6, wherein the at least one first data transmission circuit is operatively coupled to two memory devices per rank, and the first bit width is twice the second bit width.

8. The memory module of claim 6, wherein the at least one second data transmission circuit has a third bit width and each of the at least two memory devices to which the at least one second data transmission circuit is operatively coupled has a fourth bit width which is less than the third bit width.

9. The memory module of claim 8, wherein the at least one second data transmission circuit is operatively coupled to two memory devices per rank, and the third bit width is twice the fourth bit width.

10. The memory module of claim 1, wherein the corresponding positions of the at least one first data transmission circuit and the at least one second data transmission circuit are separate from one another.

11. The memory module of claim 10, wherein the corresponding positions of the at least one first data transmission circuit and the at least one second data transmission circuit are along an edge of the at least one printed circuit board such that the at least one first data transmission circuit is located substantially between the edge and at least some of the at least two memory devices operatively coupled to the at least one first data transmission circuit and the at least one second data transmission circuit is located substantially between the edge and at least some of the at least two memory devices operatively coupled to the at least one second data transmission circuit.

12. The memory module of claim 11, wherein the at least one printed circuit board comprises a connector comprising a plurality of electrical contacts which are positioned on the edge of the at least one printed circuit board and are configured to be releasably coupled to corresponding contacts of a computer system socket.

13. The memory module of claim 1, wherein a package containing the at least one first data transmission circuit is at a location spaced from a location of a package containing the at least one second data transmission circuit.

14. The memory module of claim 13, wherein a position of the at least one first data transmission circuit is generally aligned with one or more of the at least two memory devices operatively coupled to the at least one first data transmission circuit.

15. The memory module of claim 1, wherein the at least one first data transmission circuit and the at least two memory devices operatively coupled to the at least one first data transmission circuit are positioned generally along a line that is substantially perpendicular to an edge of the at least one printed circuit board.

16. The memory module of claim 13, wherein a position of the at least one first data transmission circuit is generally offset from a line defined by the positions of the at least two memory devices operatively coupled to the at least one first data transmission circuit.

17. The memory module of claim 16, wherein the line is substantially perpendicular to an edge of the at least one printed circuit board and the at least one first data transmission circuit is offset from the line in a direction generally along the edge.

18. A memory module comprising:

a plurality of memory devices;

a controller configured to receive control information from a system memory controller and to produce module control signals; and

a plurality of circuits configured to selectively isolate the plurality of memory devices from the system memory controller, wherein the circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller, wherein the circuits are distributed at corresponding positions separate from one another.

19. The memory module of claim 18, wherein the plurality of circuits is contained in a plurality of packages at locations spaced from one another.

20. The memory module of claim 19, wherein the plurality of memory devices, the controller, and the plurality of circuits are mechanically coupled to a printed circuit board having an edge, wherein the packages are positioned along the edge and between the edge and the plurality of memory devices.

21. The memory module of claim 18, wherein the circuits comprise byte-wise buffers.

22. The memory module of claim 18, wherein the each circuit of the plurality of circuits comprises:

a data terminal configurable to be operatively coupled to the system memory controller;

a first memory terminal configurable to be operatively coupled to a first group of the plurality of memory devices; and

a second memory terminal configurable to be operatively coupled to a second group of the plurality of memory devices;

wherein, when the circuit drives write data, the data terminal is operatively coupled to one of the first memory terminal and the second memory terminal; and

wherein, when the circuit merges read data, one of the first memory terminal and the second memory terminal is operatively coupled to the data terminal.

23. The memory module of claim 18, wherein the memory module is a dual in-line memory module.

24. The memory module of claim 18, wherein the plurality of memory devices comprise one or more synchronous dynamic random access memory devices.

25. A method of operating a memory module comprising a plurality of memory devices, the method comprising:

providing a data transmission circuit on a data line between a computer system memory controller and the plurality of memory devices of the memory module, the data transmission circuit comprising a byte-wise buffer;

during a write operation, enabling the data transmission circuit to drive a data signal from the computer system memory controller on one of a plurality of paths to the memory devices of the memory module; and

during a read operation, enabling the data transmission circuit to merge a plurality of data signals from the memory devices of the memory module and driving the merged data signal to the computer system memory controller.

26. The method of claim 25, further comprising providing a controller configured to receive control information from the computer system memory controller and to produce at least one module control signal in response to the control information, wherein enabling the data transmission circuit to drive a data signal comprises transmitting the at least one module control signal from the controller to the data transmission circuit.

27. The method of claim 25, further comprising providing a controller configured to receive control information from the computer system memory controller and to produce at least one module control signal in response to the control information, wherein enabling the data transmission circuit to merge a plurality of data signals comprises transmitting the at least one module control signal from the controller to the data transmission circuit.