SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE
First Claim
1. A memory module comprising:
- at least one printed circuit board;
a plurality of memory devices mechanically coupled to the at least one printed circuit board;
a control circuit mechanically coupled to the at least one printed circuit board, the control circuit configurable to receive control signals from a system memory controller and to transmit module control signals to the plurality of memory devices; and
a plurality of data transmission circuits mechanically coupled to the at least one printed circuit board and distributed at corresponding positions relative to the at least one printed circuit board, the plurality of data transmission circuits configurable to be operatively coupled to the system memory controller and configurable to receive module control signals from the control circuit,wherein at least one first data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices, at least one second data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices,wherein the at least one first data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one first data transmission circuit, and the at least one second data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one second data transmission circuit.
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Accused Products
Abstract
A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.
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Citations
27 Claims
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1. A memory module comprising:
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at least one printed circuit board; a plurality of memory devices mechanically coupled to the at least one printed circuit board; a control circuit mechanically coupled to the at least one printed circuit board, the control circuit configurable to receive control signals from a system memory controller and to transmit module control signals to the plurality of memory devices; and a plurality of data transmission circuits mechanically coupled to the at least one printed circuit board and distributed at corresponding positions relative to the at least one printed circuit board, the plurality of data transmission circuits configurable to be operatively coupled to the system memory controller and configurable to receive module control signals from the control circuit, wherein at least one first data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices, at least one second data transmission circuit of the plurality of data transmission circuits is operatively coupled to at least two memory devices of the plurality of memory devices, wherein the at least one first data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one first data transmission circuit, and the at least one second data transmission circuit is configurable to respond to the module control signals by selectively allowing or inhibiting data transmission between the system memory controller and at least one selected memory device of the at least two memory devices operatively coupled to the at least one second data transmission circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory module comprising:
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a plurality of memory devices; a controller configured to receive control information from a system memory controller and to produce module control signals; and a plurality of circuits configured to selectively isolate the plurality of memory devices from the system memory controller, wherein the circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller, wherein the circuits are distributed at corresponding positions separate from one another. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. A method of operating a memory module comprising a plurality of memory devices, the method comprising:
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providing a data transmission circuit on a data line between a computer system memory controller and the plurality of memory devices of the memory module, the data transmission circuit comprising a byte-wise buffer; during a write operation, enabling the data transmission circuit to drive a data signal from the computer system memory controller on one of a plurality of paths to the memory devices of the memory module; and during a read operation, enabling the data transmission circuit to merge a plurality of data signals from the memory devices of the memory module and driving the merged data signal to the computer system memory controller. - View Dependent Claims (26, 27)
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Specification