Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof

• US 20110016326A1
• Filed: 04/21/2010
• Published: 01/20/2011
• Est. Priority Date: 07/14/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craig, Jesse E., Stanski, Stanley B., Vento, Scott T.
• Granted Patent: US 8,484,481 B2
• Time in Patent Office: Days
• US Class Current: 713/185
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2221/2127 Bluffing

Abstract

A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.

Claims

1. A system for implementing a chip lockout protection scheme for an integrated circuit (IC) device, comprising:

an on-chip password register that stores a password externally input by a user;

an on-chip security block in communication with the password register, the security block configured to generate a chip unlock signal, the value of which depends on whether the externally input password by the user matches a correct password for the IC device;

an on-chip false data generator in communication with external data inputs to the IC device;

an input protection scheme in communication with the chip unlock signal, the input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and

an output protection scheme in communication with the false data generator and the chip unlock signal, the output protection scheme configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs of the IC device upon entry of an incorrect password;

wherein the false data generated by the false data generator is deterministic and based upon external data inputs to the IC device, thereby obfuscating whether the user has actually entered the correct password or not.

2. The system of claim 1, further comprising:

an on-chip false scan path, in addition to a real scan path;

wherein external scan-in data is gated to the real scan path by the chip unlock signal upon entry of the correct password, the external scan-in data also coupled directly to the false scan path; and

a multiplexing device controlled by the chip unlock signal, the multiplexing device configured to steer data from the real scan path to an external scan-out output of the IC device upon entry of the correct password, and configured to steer data from the false scan path to the external scan-out output of the IC device upon entry of an incorrect password.

3. The system of claim 2, further comprising random inserted logic between parallel scan chains included within the false scan path, wherein the random inserted logic does is not equivalent to logic included within the real scan path.

4. The system of claim 1, further comprising a non-volatile password storage device in communication with the security block, the non-volatile password device containing one or more correct passwords for the IC device.

5. The system of claim 4, further comprising a password generator in communication with the password storage device and the security block, the password generator configured to generate the one or more passwords for the IC device.

6. The system of claim 5, wherein the password generator employs a password rotation scheme.

7. The system of claim 1, wherein the false data generator further comprises a linear shift feedback register (LFSR).

8. The system of claim 7, wherein the false data generator further comprises a random reduction logic cone coupled to the external data inputs, the random reduction logic cone configured to shift a reduction of the external data inputs into the LFSR.

9. The system of claim 8, wherein the false data generator is in communication with the password register.

10. The system of claim 9, wherein the false data generator generates unique but deterministic false data for different incorrect passwords.

11. A method for implementing a chip lockout protection scheme for an integrated circuit (IC) device, the method comprising:

inserting an on-chip password register that stores a password externally input by a user;

inserting an on-chip security block in communication with the password register, the security block configured to generate a chip unlock signal, the value of which depends on whether the externally input password by the user matches a correct password for the IC device;

inserting an on-chip false data generator in communication with external data inputs to the IC device;

inserting an input protection scheme in communication with the chip unlock signal, the input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and

inserting an output protection scheme in communication with the false data generator and the chip unlock signal, the output protection scheme configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs of the IC device upon entry of an incorrect password;

wherein the false data generated by the false data generator is deterministic and based upon external data inputs to the IC device, thereby obfuscating whether the user has actually entered the correct password or not.

12. The method of claim 11, further comprising:

inserting an on-chip false scan path, in addition to a real scan path;

wherein external scan-in data is gated to the real scan path by the chip unlock signal upon entry of the correct password, the external scan-in data also coupled directly to the false scan path; and

inserting a multiplexing device controlled by the chip unlock signal, the multiplexing device configured to steer data from the real scan path to an external scan-out output of the IC device upon entry of the correct password, and configured to steer data from the false scan path to the external scan-out output of the IC device upon entry of an incorrect password.

13. The method of claim 12, further comprising inserting random logic between parallel scan chains included within the false scan path, wherein the random inserted logic does is not equivalent to logic included within the real scan path.

14. The method of claim 11, further comprising inserting a non-volatile password storage device in communication with the security block, the non-volatile password device containing one or more correct passwords for the IC device.

15. The method of claim 14, further comprising inserting a password generator in communication with the password storage device and the security block, the password generator configured to generate the one or more passwords for the IC device.

16. The method of claim 15, wherein the password generator employs a password rotation scheme.

17. The method of claim 11, wherein the false data generator further comprises a linear shift feedback register (LFSR).

18. The method of claim 17, wherein the false data generator further comprises a random reduction logic cone coupled to the external data inputs, the random reduction logic cone configured to shift a reduction of the external data inputs into the LFSR.

19. The method of claim 18, wherein the false data generator is in communication with the password register.

20. The method of claim 19, wherein the false data generator generates unique but deterministic false data for different incorrect passwords.