PIXEL ARRAY

• US 20110017994A1
• Filed: 10/08/2009
• Published: 01/27/2011
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lee, Kuo-Hsien, Kuo, Jing-Tin
• Granted Patent: US 7,982,219 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A pixel array includes scan lines, data lines, and pixels. Each pixel arranged in the n^th row includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In the first sub-pixel, a first gate and a first drain of a first transistor are connected to the (n−1)^th scan line and a first pixel electrode, respectively. In the second sub-pixel, a second gate of a second transistor is connected to the n^th scan line, and a second drain is connected to a second pixel electrode and a first source of the first transistor. In the third sub-pixel, a third gate of a third transistor is connected to the (n+1)^th scan line, a third drain is connected to a third pixel electrode and a second source of the second transistor, and a third source is connected to one of the data lines.

Claims

1. A pixel array, comprising:

a plurality of scan lines;

a plurality of data lines intersecting the scan lines;

a plurality of pixels connected to the scan lines and the data lines, each of the pixels arranged in an n^th row comprising;

a first sub-pixel comprising a first transistor and a first pixel electrode, wherein a first gate of the first transistor is connected to an (n−

1)^th scan line, and a first drain of the first transistor is connected to the first pixel electrode

a second sub-pixel comprising a second transistor and a second pixel electrode, wherein a second gate of the second transistor is connected to an n^th scan line, and a second drain of the second transistor is connected to the second pixel electrode and a first source of the first transistor; and

a third sub-pixel comprising a third transistor and a third pixel electrode, wherein a third gate of the third transistor is connected to an (n+1)^th scan line, a third drain of the third transistor is connected to the third pixel electrode and a second source of the second transistor, and a third source of the third transistor is connected to one of the data lines.

2. The pixel array as claimed in claim 1, wherein the pixels together connected to one of the data lines are distributed at the same side of the one of the data lines.

3. The pixel array as claimed in claim 1, wherein each of the data lines extends along a column direction in a zigzag manner, and each of the data lines comprises:

a plurality of first conductive lines extending along a row direction; and

a plurality of second conductive lines extending along the column direction, wherein the first conductive lines and the second conductive lines are alternately connected.

4. The pixel array as claimed in claim 3, wherein a length of each of the first conductive lines is equal to a width of one of the pixels, and a length of each of the second conductive lines is equal to a length of one of the pixels.

5. The pixel array as claimed in claim 3, wherein among the pixels arranged in the same column, some of the pixels arranged in odd rows are connected to one of the data lines, and the other pixels arranged in even rows are connected to another one of the data lines.

6. The pixel array as claimed in claim 1, wherein the first source is directly connected to the second drain.

7. The pixel array as claimed in claim 1, wherein the second source is connected to the third drain through the third pixel electrode.

8. The pixel array as claimed in claim 3, wherein in each of the pixels arranged in the n^th row, the first pixel electrode, the second transistor, the second pixel electrode, the third transistor, and the third pixel electrode are located between the n^th scan line and the (n+1)^th scan line, and the first transistor is located between the n^th scan line and the (n−

1)^th scan line.

9. The pixel array as claimed in claim 1, wherein each of the scan lines extends along a row direction in a zigzag manner, and each of the scan lines comprises:

a plurality of third conductive lines extending along the row direction; and

a plurality of fourth conductive lines extending along a column direction, wherein the third conductive lines and the fourth conductive lines are alternately connected.

10. The pixel array as claimed in claim 9, wherein the fourth conductive lines are located between the first sub-pixel and the second sub-pixel and between the second sub-pixel and the third sub-pixel in the same pixel.

11. The pixel array as claimed in claim 9, wherein the fourth conductive lines are located between the second sub-pixel and the first sub-pixel in the same pixel.

12. The pixel array as claimed in claim 9, wherein in each of the pixels arranged in the n^th row, the first transistor, the first pixel electrode, the second transistor, the second pixel electrode, the third transistor, and the third pixel electrode are located between the n^th scan line and the (n+1)^th scan line.