SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

• US 20110018033A1
• Filed: 03/26/2009
• Published: 01/27/2011
• Est. Priority Date: 03/26/2008
• Status: Active Grant

• Current Assignee: Sumitomo Chemical Company Limited, University of Tokyo
• Original Assignee: Sumitomo Chemical Company Limited, University of Tokyo
• Inventors: Ichikawa, Osamu, Takagi, Shinichi, Takenaka, Mitsuru, Hata, Masahiko
• Granted Patent: US 8,431,459 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Abstract

It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.

Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

Claims

1. A semiconductor wafer comprising:

a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and

a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer.

2. The semiconductor wafer according to claim 1, wherein the first semiconductor layer does not contain aluminum.

3. The semiconductor wafer according to claim 1, comprising a 3-5 compound semiconductor that is formed to contact the first semiconductor layer, lattice matches or pseudo-lattice matches with InP, and has an electron infinity higher than that of InP.

4. The semiconductor wafer according to claim 1, wherein

the second semiconductor layer contains aluminum.

5. The semiconductor wafer according to claim 4, wherein

the second semiconductor layer is In_xAl_1-xAs, where x is a value between 0 and 1.

6. A semiconductor device comprising:

a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP;

an oxide layer obtained by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is formed to contact the first semiconductor layer and that is a group 3-5 compound semiconductor layer lattice matching or pseudo-lattice matching with InP; and

a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

7. The semiconductor device according to claim 6, wherein

the oxide layer is a control electrode insulating layer formed between the first semiconductor layer and the control electrode, or a buried oxide layer formed to be buried farther on the wafer side than the first semiconductor layer.

8. The semiconductor device according to claim 6, wherein

a non-oxidized portion of the second semiconductor layer remains in the same layer as the oxide layer, and

the semiconductor device comprises:

an ohmic layer that is formed above the non-oxidized portion of the second semiconductor layer and that includes an open portion in a region where the oxide layer is formed; and

a pair of input/output electrodes that are formed above the ohmic layer and that supply current flowing through the channel.

9. The semiconductor device according to claim 8, wherein the control electrode is formed on the oxide layer within the open portion.

10. The semiconductor device according to claim 8, wherein

the ohmic layer is a group 3-5 compound semiconductor layer that does not contain aluminum and that lattice matches or pseudo-lattice matches with InP.

11. The semiconductor device according to claim 10, wherein the ohmic layer is doped to be p-type or n-type.

12. A method of manufacturing a semiconductor device, comprising:

preparing a semiconductor wafer including (i) a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP and (ii) a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP;

forming an oxide layer by selectively oxidizing the second semiconductor layer relative to the first semiconductor layer; and

forming a control electrode above the oxide layer.

13. The method of manufacturing a semiconductor device according to claim 12, further comprising:

after preparing the semiconductor wafer, forming an ohmic layer that covers the second semiconductor layer; and

forming an open portion in the ohmic layer to expose the second semiconductor layer at a bottom of the open portion, wherein

forming the oxide layer includes selectively forming the oxide layer in the open portion by oxidizing the second semiconductor layer exposed in the open portion.

14. The method of manufacturing a semiconductor device according to claim 13, wherein forming the oxide layer includes exposing, in an oxidation atmosphere, the second semiconductor layer exposed by the open portion with the ohmic layer as a mask to form the oxide layer in a self-aligning manner with the mask.

15. The method of manufacturing a semiconductor device according to claim 13, wherein the ohmic layer is a p-type or n-type group 3-5 compound semiconductor layer that does not contain aluminum and that lattice matches or pseudo-lattice matches with InP.

16. The method of manufacturing a semiconductor device according to claim 12, wherein forming the oxide layer includes using wet oxidation to form the oxide layer.

17. A semiconductor wafer comprising:

a first semiconductor that is formed of a group 3-5 compound not containing arsenic and that functions as a channel of a transistor; and

a second semiconductor that is disposed above the first semiconductor and that is oxidized in an oxidation atmosphere to become an insulator.

18. The semiconductor wafer according to claim 17, wherein the first semiconductor and the second semiconductor lattice match or pseudolattice match with InP.

19. The semiconductor wafer according to claim 17, wherein the first semiconductor is not oxidized in an oxidation atmosphere.

20. The semiconductor wafer according to claim 17, wherein the second semiconductor can be selectively oxidized by arranging, on the surface thereof, a mask that covers a non-oxidized region and exposes an oxidized region.