Shield Contacts in a Shielded Gate MOSFET

• US 20110018059A1
• Filed: 07/24/2009
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean E., Dunn, Dixie, Thorup, Paul, Gruenhagen, Michael D.
• Granted Patent: US 7,952,141 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

Claims

1. A semiconductor structure comprising:

an active region comprising trenches extending into a semiconductor region, each trench including a shield electrode in a bottom portion of the trench, a gate electrode in an upper portion of the trench over the shield electrode, and an inter-electrode dielectric layer extending between the shield electrode and the gate electrode;

a shield contact region adjacent to the active region, the shield contact region comprising at least one contact trench extending into the semiconductor region, wherein the shield electrode from at least one of the trenches in the active region extends along a length of the contact trench; and

an interconnect layer extending over the active region and the shield contact region, wherein in the active region the interconnect layer is isolated from the gate electrode in each of the trenches by a dielectric layer and the interconnect layer contacts mesa surfaces of the semiconductor region adjacent to the trenches, and in the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

2. The semiconductor structure of claim 1 wherein at least one of the trenches in the active region extends into the shield contact region and is contiguous with the contact trench.

3. The semiconductor structure of claim 1 wherein at least one of the trenches in the active region does not extend into the shield contact region.

4. The semiconductor structure of claim 1 wherein each of the trenches in the active region extends in a first direction, the active region further comprising at least one cross trench extending substantially perpendicular to the trenches, wherein a gate electrode in the cross trench is contiguous with the gate electrode in at least one of the trenches.

5. The semiconductor structure of claim 1 wherein the shield electrode in the shield contact region extends from a bottom portion of the contact trench to an upper portion of the contact trench.

6. The semiconductor structure of claim 1 wherein in the shield contact region the interconnect layer contacts the mesa surfaces of the semiconductor region adjacent to the contact trench to form Schottky contacts therebetween.

7. The semiconductor structure of claim 1 wherein the shield contact region comprises a plurality of contact trenches separated by the mesa surfaces of the semiconductor region, and wherein Schottky contacts are formed between the interconnect layer and a portion of the mesa surfaces.

8. The semiconductor structure of claim 1 wherein in the active region Schottky contacts are formed between the interconnect layer and a portion of the mesa surfaces.

9. The semiconductor structure of claim 1 wherein the active region further comprises a body region in the semiconductor region and a source region in the body region adjacent each trench.

10. A semiconductor structure comprising:

first and second active regions each comprising trenches extending into a semiconductor region, wherein each trench includes a shield electrode in a bottom portion of the trench, a gate electrode in an upper portion of the trench over the shield electrode, and an inter-electrode dielectric layer extending between the shield electrode and the gate electrode;

a shield contact region between the first and second active regions, the shield contact region comprising at least one contact trench extending into the semiconductor region, wherein the shield electrode from at least one of the trenches in the first active region extends along a length of the contact trench; and

an interconnect layer extending over the first and second active regions and the contact region, wherein in the first and second active regions the interconnect layer is isolated from the gate electrode in each of the trenches by a dielectric layer and the interconnect layer contacts mesa surfaces of the semiconductor region adjacent to the trenches, and in the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.

11. The semiconductor structure of claim 10 wherein at least one of the trenches in the first active region extends into the shield contact region and is contiguous with the contact trench.

12. The semiconductor structure of claim 10 wherein the shield electrode in the shield contact region extends from a bottom portion of the contact trench to an upper portion of the contact trench.

13. The semiconductor structure of claim 10 wherein in the shield contact region the interconnect layer contacts the mesa surfaces of the semiconductor region adjacent to the contact trench to form Schottky contacts therebetween.

14. The semiconductor structure of claim 10 wherein the shield contact region comprises a plurality of contact trenches separated by the mesa surfaces of the semiconductor region, and wherein Schottky contacts are formed between the interconnect layer and a portion of the mesa surfaces.

15. The semiconductor structure of claim 10 wherein in the first active region Schottky contacts are formed between the interconnect layer and a portion of the mesa surfaces.

16. The semiconductor structure of claim 10 wherein the first and second active regions further comprises body regions in the semiconductor region and source regions in the body regions adjacent each trench.

17. A method of forming a shielded gate MOSFET, the method comprising:

forming trenches in a semiconductor region;

forming a shield electrode in each trench;

forming gate electrodes in a portion of the trenches, the portion of the trenches forming an active region, wherein each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric; and

forming an interconnect layer extending over the trenches, the interconnect layer being isolated from the gate electrodes in the active region by a dielectric layer, the interconnect layer contacting the shield electrodes in a shield contact region separate from the active region and contacting mesa surfaces between adjacent trenches in the shield contact region.

18. The method of claim 17 further comprising:

forming Schottky contacts between the interconnect layer and the mesa surfaces extending between adjacent trenches in the shield contact region.

19. The method of claim 17 further comprising:

forming Schottky contacts between the interconnect layer and a portion of the mesa surfaces extending between adjacent trenches in the shield contact region.

20. The method of claim 17 wherein the interconnect layer contacts mesa surfaces between adjacent trenches in the active region, the method further comprising:

forming Schottky contacts between the interconnect layer and a portion of the mesa surfaces extending between adjacent trenches in the active region.