NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
First Claim
1. A non-volatile programmable memory cell formed in a semiconductor substrate of a first conductivity type and comprising:
- a non-volatile MOS transistor of a second conductivity type formed in a first semiconductor region of the first conductivity type and coupled between a first power supply potential and an output node;
a volatile MOS transistor of the first conductivity type formed in a semiconductor region of the second conductivity type and coupled between the output node and a second power supply potential; and
a volatile MOS switch transistor of the second conductivity type formed in a second semiconductor region of the first conductivity type and coupled to the output node;
wherein the first and second semiconductor regions of the first conductivity type are electrically isolated from one another.
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Accused Products
Abstract
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
22 Citations
1 Claim
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1. A non-volatile programmable memory cell formed in a semiconductor substrate of a first conductivity type and comprising:
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a non-volatile MOS transistor of a second conductivity type formed in a first semiconductor region of the first conductivity type and coupled between a first power supply potential and an output node; a volatile MOS transistor of the first conductivity type formed in a semiconductor region of the second conductivity type and coupled between the output node and a second power supply potential; and a volatile MOS switch transistor of the second conductivity type formed in a second semiconductor region of the first conductivity type and coupled to the output node; wherein the first and second semiconductor regions of the first conductivity type are electrically isolated from one another.
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Specification