SEMICONDUCTOR DEVICE

• US 20110018101A1
• Filed: 07/15/2010
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: OMORI, Tomoyuki
• Granted Patent: US 8,330,233 B2
• Time in Patent Office: Days
• US Class Current: 257/548
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n⁻ type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p⁻ type columnar regions formed in the n⁻ drift region 12 of the cell region 2, a plurality of p⁻ type columnar resistance improvement regions 23n formed in the n⁻ type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p⁻ type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.

Claims

1. A semiconductor device comprising:

a cell region formed with semiconductor elements;

a periphery region formed on a periphery of the cell region;

a first conduction type first conduction type region formed in the cell region and the periphery region;

a plurality of second conduction type first columnar regions formed in the first conduction type region of the cell region;

a plurality of second conduction type second columnar regions formed in the first conduction type region of the periphery region; and

a plurality of second conduction type electrical field buffer regions formed on an upper part of the second columnar region;

wherein an interval between the electrical field buffer region and an adjacent electrical field buffer region is different between an interior side and an exterior side.

2. The semiconductor device according to claim 1, wherein an interval between the electrical field buffer region and the adjacent electrical field buffer region on the interior side of the periphery region is smaller than an interval between the electrical field buffer region and an the adjacent electrical field buffer region on the exterior side of the cell region.

3. The semiconductor device according to claim 2, wherein an interval between the electrical field buffer region and the adjacent electrical field buffer region becomes gradually smaller from an interior side of the periphery region approaching an exterior side.

4. The semiconductor device according to claim 2, wherein a width of the electrical buffer region becomes gradually smaller from an interior side of the periphery region approaching an exterior side.

5. The semiconductor device according to claim 3, wherein a width of the electrical buffer region becomes gradually smaller from an interior side of the periphery region approaching an exterior side.

6. The semiconductor device according to claim 2, wherein a depth of the electrical buffer region becomes gradually shallower approaching an exterior side of the periphery region.

7. The semiconductor device according to claim 3, wherein a depth of the electrical buffer region becomes gradually shallower approaching an exterior side of the periphery region.

8. The semiconductor device according to claim 4, wherein a depth of the electrical buffer region becomes gradually shallower approaching an exterior side of the periphery region.

9. The semiconductor device according to claim 1, wherein a distance between the first columnar region and the adjacent first columnar region and a distance between the second columnar region and the adjacent second columnar region is equal.

10. The semiconductor device according to claim 2, wherein a distance between the first columnar region and the adjacent first columnar region and a distance between the second columnar region and the adjacent second columnar region is equal.

11. The semiconductor device according to claim 3, wherein a distance between the first columnar region and the adjacent first columnar region and a distance between the second columnar region and the adjacent second columnar region is equal.

12. The semiconductor device according to claim 4, wherein a distance between the first columnar region and the adjacent first columnar region and a distance between the second columnar region and the adjacent second columnar region is equal.

13. The semiconductor device according to claim 5, wherein a distance between the first columnar region and the adjacent first columnar region and a distance between the second columnar region and the adjacent second columnar region is equal.