SYSTEM FOR EMBEDDED VIDEO TEST PATTERN GENERATION

• US 20110019006A1
• Filed: 07/19/2010
• Published: 01/27/2011
• Est. Priority Date: 07/21/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Smith, Greg, Varga, Gabriel
• Granted Patent: US 8,675,076 B2
• Time in Patent Office: Days
• US Class Current: 348/181
• CPC Class Codes: H04N 17/04 for receivers

Abstract

In accordance with some embodiments of the invention, a video processing circuit can include a synchronization generator to generate a clock signal from an input video stream; and a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles. In accordance with some embodiments of the present invention, a video processing system may include an video input capture circuit; a video input processing circuit including a synchronization generator and a test pattern generator; a video scaling circuit; a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and a video output circuit including a cyclical redundancy check circuit.

Claims

1. A video processing circuit, comprising:

a synchronization generator to generate a clock signal from an input video stream; and

a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles.

2. The video processing circuit of claim 1 wherein the synchronization generator comprises:

a test pattern generator clock;

a pixel rate generator;

a video timing generator to provide the clock signal using the pixel rate signal; and

a multiplexer to select between a clock signal from an input video stream and the clock signal provided by the video timing generator to provide a clock signal to the video processing circuit.

3. The video processing circuit of claim 2 wherein the test pattern generator comprises:

a pseudo random number generator to provide variable test patterns;

a register to provide initial values to the test patterns;

an accumulator to accumulate values from previous cycles; and

a mode configuration bit to select a test pattern.

4. The video processing circuit of claim 3 wherein

the circuit provides the test pattern to an output video stream;

and the circuit further comprises a lookup table to obtain a digital signature from the input video frame and the test pattern.

5. The video processing circuit of claim 1 further comprising a controller circuit to test the clock signal provided to the video processing circuit.

6. A video processing system, comprising:

an video input capture circuit;

a video input processing circuit comprising a synchronization generator and a test pattern generator;

a video scaling circuit;

a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and

a video output circuit comprising a cyclical redundancy check circuit.

7. The video processing system of claim 6 wherein the synchronization generator further comprises:

a test pattern generator clock;

a pixel rate generator providing a data enable signal; and

a video timing generator to provide a clock signal using the pixel rate signal;

a multiplexer to select between a clock signal from an input video stream and the clock signal provided by the video timing generator.

8. The video processing system of claim 6, further wherein:

the test pattern generator generates a test pattern over a number of cycles; and

the cyclical redundancy check circuit provides a unique digital signature for each video frame passed through the system.

9. The video processing system of claim 8 wherein the test pattern generator further comprises:

a pseudo random number generator to provide variability to the test patterns;

at least one register to provide initial values to generate the test patterns;

at least one accumulator to provide values from previous cycles, and

a mode configuration bit to select a test pattern; and

a lookup table to obtain a digital signature from the input video frame and the test pattern.

10. The system as in claim 6 further wherein

The video input processing circuit performs noise reduction and contrast enhancement to the input video signal.

11. The system as in claim 6 further comprising

a memory controller unit coupled to the video input processing circuit, the video scaling circuit, the video merging circuit, and the video output circuit;

the memory controller further comprising;

at least one test pattern generator; and

at least one cyclic redundancy check (CRC) circuit; and

a computer processor unit (CPU) coupled to the memory controller unit to control the forming of test patterns;

12. The system as in claim 11 where the CPU further comprises:

at least one test pattern generator to provide test patterns to the memory controller; and

at least one cyclic redundancy check (CRC) circuit to create unique digital signatures for each video frame and each test pattern.

13. The system as in claim 6 further wherein the video merging circuit comprises an OSD to control an image superimposed onto the video signal provided by the video scaling circuit.

14. The system as in claim 13 further wherein the image superimposed onto the video signal provided by the video scaling circuit is a test pattern provided by the test pattern generator in the memory controller circuit.

15. A method to generate test patterns comprising the steps of:

generating a pseudo random number to provide variability to the test patterns;

providing initial values to at least one register to generate the test patterns;

determining a number of cycles to use for generating the test patterns;

providing values from previous cycles using at least one accumulator;

selecting a test pattern using a mode configuration bit; and

obtaining a digital signature from an input video frame and the test pattern by using a lookup table.