LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF

• US 20110019140A1
• Filed: 10/16/2009
• Published: 01/27/2011
• Est. Priority Date: 07/22/2009
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jae-Hoon, Min, Tae-Gee, Shim, Yi-Seop, Kwon, Seong-Gyu
• Application Number:
  US12/580,408
• Publication Number:
  US 20110019140A1
• Time in Patent Office: Days
• US Class Current: 349/138
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/133519 Overcoatings
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A display panel according to the present invention includes a first insulating substrate with a gate line and a data line formed thereon. A thin film transistor is connected to the gate line and the data line and a partition is formed according to the gate line and the data line defining a color filter filling region. Color filter is formed as a convex shape since both circumferences of upper portion and lower portion of the partition are larger than that of center portion. A color filter is formed in the filling region. A passivation layer is formed on the color filter and the partition and a pixel electrode on the passivation layer connected to the thin film transistor through a contact hole punching the passivation layer and the color filter.

Claims

1. A display panel comprising:

a first insulating substrate;

a gate line and a data line formed on the insulating substrate and insulated from and intersecting each other;

a thin film transistor connected to the gate line and the data line;

a partition formed according to the gate line and the data line;

a color filter formed in the filling region defined by the partition;

a passivation layer formed on the color filter and the partition; and

a pixel electrode formed on the passivation layer and connected to the thin film transistor through a contact hole formed in the passivation layer and the color filter,

wherein both circumferences of upper portion and lower portion of the partition are larger than that of center portion

2. A display panel of claim 1, wherein the color filter is formed on the first insulating substrate

3. A display panel of claim 1, wherein the partition is formed on the first insulating substrate

4. A display panel of claim 1,

a second insulating substrate facing to the first insulating substrate

a liquid crystal layer interposed therebetween

a spacer between the first and the second substrate

wherein the spacer is formed with the partition in the same process step

5. A display panel of claim 1,

an upper passivation layer formed on the color filter

a pixel electrode formed on the upper passivation

wherein the upper passivation layer is formed to the thickness higher than the highest position of the color filter

6. A display panel of claim 1, wherein

a lower passivation layer is formed on the thin film transistor and the gate line

7. A display panel comprising:

a first insulating substrate;

a gate line and a data line formed on the insulating substrate and insulated from and intersecting each other;

a thin film transistor connected to the gate line and the data line;

a second insulating substrate;

a partition formed on the second insulating substrate;

a color filter formed in the filling region defined by the partition;

wherein both circumferences of upper portion and lower portion of the partition are larger than that of center portion

8. A display panel of claim 7,

a second insulating substrate facing to the first insulating substrate

a liquid crystal layer interposed therebetween

a spacer between the first and the second substrate

wherein the spacer is formed with the partition in the same process step

9. A manufacturing method of display panel, comprising:

forming a gate line including a gate electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor and an ohmic contact layer on the gate insulating layer;

forming a data line including a source electrode and a drain electrode on the ohmic contact layer;

forming a lower passivation layer on the data line and the drain electrode;

forming a partition with a sandglass shape according to the gate line and the data line on the lower passivation layer;

forming a color filter in a filling region defined by the partition;

forming an upper passivation layer on the color filter;

simultaneously etching the upper passivation layer and the color filter to form a contact hole exposing the drain electrode; and

forming a pixel electrode connected to the drain electrode through the contact hole on is the upper passivation layer.