FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS
First Claim
1. An apparatus comprising:
- a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and third and fourth redundancy interleave groups of redundant columns;
first and second data latches configured to store data read from the first and second interleave groups of regular columns, respectively;
third and fourth redundant data latches configured to store data read from the third and fourth redundancy interleave groups of redundant columns, respectively;
a multiplexer comprising at least four inputs, each of which is electrically coupled to a respective one of the first and second data latches and the third and fourth redundant data latches; and
a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme.
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Accused Products
Abstract
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
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Citations
20 Claims
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1. An apparatus comprising:
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a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and third and fourth redundancy interleave groups of redundant columns; first and second data latches configured to store data read from the first and second interleave groups of regular columns, respectively; third and fourth redundant data latches configured to store data read from the third and fourth redundancy interleave groups of redundant columns, respectively; a multiplexer comprising at least four inputs, each of which is electrically coupled to a respective one of the first and second data latches and the third and fourth redundant data latches; and a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An electronic device, comprising:
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a memory block comprising a regular section and a repair section, wherein the regular section further comprises even-numbered columns and odd-numbered columns alternating with each other, wherein the repair section further comprises even-numbered redundant columns and odd-numbered redundant columns alternating with each other; a first data latch electrically coupled to the even-numbered columns, but not to the odd-numbered columns, in the regular section; a second data latch electrically coupled to the odd-numbered columns, but not to the even-numbered columns, in the regular section; a first redundant data latch electrically coupled to the even-numbered redundant columns, but not to the odd-numbered redundant columns, in the repair section; a second redundant data latch electrically coupled to the odd-numbered redundant columns, but not to the odd-numbered columns, in the repair section; a multiplexer comprising first to fourth inputs electrically coupled to the first data latch, the second data latch, the first redundant data latch, and the second redundant data latch, respectively; and a control circuit for the multiplexer, wherein the control circuit is configured provide control signals to the multiplexer such that the multiplexer outputs data in an alternating manner from at least one of the first or second data latches and at least one of the third or fourth redundant data latches to perform an interleaved read scheme. - View Dependent Claims (13, 14, 15, 16)
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17. A method of reading data from a flash memory device comprising a memory block, wherein the memory block includes a plurality of rows and a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells, the plurality of columns including first and second interleave groups of regular columns and first and second redundancy interleave groups of redundant columns, each of the rows comprising a word line coupled to a respective row of the memory cells, the method comprising:
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latching a first set of data digits that are sequentially read from the first interleave group of regular columns in the memory block; latching a second set of data digits that are sequentially read from the second interleave group of regular columns in the memory block; latching a data digit from a redundant column in the first redundancy interleave group of redundant columns in the memory block, the redundant column being configured to replace a defective column in the first interleave group of regular columns; outputting the latched first and second sets of data digits via first and second lines, respectively, to a multiplexer; outputting the latched data digit from the redundant column via a third line to the multiplexer; and outputting the first and second sets of data digits in an alternating manner from the multiplexer while outputting the data digit from the redundant column from the multiplexer between two immediately subsequent data digits in the second set. - View Dependent Claims (18, 19, 20)
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Specification