Semiconductor Device and Method of Fabricating the Same

• US 20110020993A1
• Filed: 06/30/2010
• Published: 01/27/2011
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Park, Jong-Man, Yamada, Santoru
• Granted Patent: US 8,169,074 B2
• Time in Patent Office: Days
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first interconnection disposed on a substrate. The interconnection includes a first silicon interconnection region and a first metal interconnection region sequentially stacked on the substrate. A second interconnection includes a second silicon interconnection region and a second metal interconnection region that are stacked sequentially. The second silicon interconnection region has a lower resistivity than the first silicon interconnection region.

Claims

1-14. -14. (canceled)

15-22. -22. (canceled)

23. A semiconductor device comprising:

a first interconnection including a first silicon interconnection region and a first metal interconnection region stacked sequentially on a substrate; and

a second interconnection including a second silicon interconnection region and a second metal interconnection region stacked sequentially on the substrate,

wherein the second silicon interconnection region is disposed at substantially the same level as the first silicon interconnection region and has a lower resistivity than the first silicon interconnection region.

24. The device of claim 23, wherein the first silicon interconnection region is formed of undoped silicon or intrinsic silicon, and the second silicon interconnection region is formed of doped silicon.

25. The device of claim 23, wherein the first and second silicon interconnection regions are formed of doped silicon of the same conductivity type, and the second silicon interconnection region is formed of doped silicon having a higher dopant concentration than the first silicon interconnection region.

26. The device of claim 23, further comprising a doped silicon buffer region interposed between the first silicon interconnection region and the first metal interconnection region and having a lower resistivity than the first silicon interconnection region.

27. The device of claim 23, wherein the first silicon interconnection region has a smaller width than the second silicon interconnection region.

28. A semiconductor device comprising:

a semiconductor substrate having first and second circuit regions;

a first MOS transistor disposed on the first circuit region of the semiconductor substrate and including a first gate structure and first source and drain regions;

a contact region electrically connected to one of the first source and drain regions;

a first silicon interconnection connected to the contact region and having a higher resistivity than the contact region;

a first metal interconnection region disposed on the contact region and the first silicon interconnection region;

a second silicon interconnection region disposed on the second circuit region of the semiconductor substrate and having a lower resistivity than the first silicon interconnection region; and

a second metal interconnection region disposed on the second silicon interconnection region.

29. The device of claim 28, wherein the first MOS transistor comprises:

first source and drain regions disposed in a first active region defined by an isolation region formed in the semiconductor substrate, the first source and drain regions spaced apart from each other; and

a first gate structure configured to partially fill a gate trench that runs across the first active region between the first source and drain regions and extends to the isolation region.

30. The device of claim 29, wherein the first gate structure partially fills the gate trench disposed across the first active region and extends to the isolation region to cover sidewalls of the first active region at a lower level than a bottom region of the gate trench of the first active region.

31. The device of claim 28, further comprising a second MOS transistor disposed on the second circuit region of the semiconductor substrate and including a second gate structure and second source and drain regions,

wherein the second MOS transistor includes:

a second gate dielectric layer and a second gate structure stacked sequentially on a second active region defined by the isolation region disposed in the semiconductor substrate; and

second source and drain regions disposed in the second active region on both sides of the second gate structure,

wherein the second gate structure includes the second silicon interconnection region and the second metal interconnection region.

32. The device of claim 28, wherein the second silicon interconnection region is disposed at substantially the same level with the first silicon interconnection region, and the second metal interconnection region is formed of the same material as the first metal interconnection region.

33. The device of claim 28, wherein the first and second silicon interconnection regions are formed of doped silicon of the same conductivity type, and the second silicon interconnection region is formed of doped silicon having a higher dopant concentration than the first silicon interconnection region.

34. The device of claim 28, wherein the contact region is formed of doped silicon or the same material as the first metal interconnection region.

35. The device of claim 28, wherein the first silicon interconnection region is formed of undoped silicon or intrinsic silicon.

36. The device of claim 28, further comprising a doped silicon buffer region interposed between the first silicon interconnection region and the first metal interconnection region and having a lower resistivity than the first silicon interconnection region.