MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20110020994A1
• Filed: 07/27/2009
• Published: 01/27/2011
• Est. Priority Date: 07/27/2009
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsieh, Chao-Ching, Lin, Chun-Hsien
• Granted Patent: US 7,915,127 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer.

Claims

1. A method of forming a semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate, wherein the gate structure comprises a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer sequentially formed on the substrate;

forming a spacer on a sidewall of the gate structure;

forming source/drain regions in the substrate beside the gate structure;

forming an interlayer dielectric layer over the substrate;

removing a portion of the interlayer dielectric layer to expose a surface of the mask layer;

sequentially removing the mask layer and the polysilicon layer to expose a surface of the wetting layer; and

performing a selective chemical vapor deposition (CVD) process, so as to bottom-up deposit a metal layer from the surface of the wetting layer.

2. The method of claim 1, wherein the gate structure further comprises an insulation layer formed between the substrate and the high-k layer.

3. The method of claim 1, wherein the metal layer comprises Al.

4. The method of claim 3, wherein a precursor for performing the selective CVD process comprises Alpis-3 ((BH₄(AlH₂N(CH₃)₃), dimethylethylamine alane (DMEAA) or dimethyaluminum hydride (DMAH).

5. The method of claim 4, wherein the wetting layer comprises Ti, TiAl_x, Ti rich TiN, Al or a combination thereof.

6. The method of claim 1, wherein the step of forming the wetting layer comprises performing a physical vapor deposition (PVD) process.

7. The method of claim 1, wherein the step of forming the wetting layer comprises performing a CVD process.

8. The method of claim 1, wherein the work function metal layer comprises TiN, TaC, TaCNO, TaCN, TiAl_x or TaN.

9. The method of claim 1, wherein the gate structure further comprises a middle layer formed between the work function metal layer and the wetting layer, and the middle layer is for adjusting a work function value of the work function metal layer.

10. The method of claim 9, wherein the middle layer and the work function metal layer comprise different materials.

11. The method of claim 10, wherein the middle layer comprises Ti rich TiN or Ti rich TiAl_x.

12. The method of claim 9, wherein the step of forming the middle layer comprises performing a PVD process.

13. The method of claim 9, wherein the step of forming the middle layer comprises performing a CVD process.

14. The method of claim 1, wherein the step of removing the portion of the interlayer dielectric layer comprises performing a chemical mechanical polishing (CMP) process.

15. The method of claim 1, wherein the step of removing the portion of the interlayer dielectric layer comprises performing an etching back process.

16. The method of claim 1, wherein the high-k layer comprises HfO₂, ZrO₂, Al₂O₃, AlN, TiO₂, La₂O₃, Y₂O₃, Gd₂O₃, Ta₂O₅ or a combination thereof.

17. The method of claim 1, further comprising forming a stress layer over the substrate after the step of forming the source/drain regions and before the step of forming the interlayer dielectric layer.

18. The method of claim 17, wherein the stress layer comprises silicon nitride.

19. The method of claim 1, wherein the source/drain regions are doped regions.

20. The method of claim 1, wherein the source/drain regions are epitaxial layers.