Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications

• US 20110021008A1
• Filed: 07/22/2009
• Published: 01/27/2011
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: RANA, Virendra V., Bachrach, Robert Z.
• Granted Patent: US 7,981,778 B2
• Time in Patent Office: Days
• US Class Current: 438/486
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1872 Recrystallisation
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 117/10 Apparatus

Abstract

Embodiments of the present invention provide a method for converting a doped amorphous silicon layer deposited onto a crystalline silicon substrate into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited. Additional embodiments of the present invention provide depositing a dielectric passivation layer onto the amorphous silicon layer prior to the conversion. A temperature gradient is provided at a temperature and for a time period sufficient to provide a desired p-n junction depth and dopant profile.

Claims

1. A method of heat treating a crystalline silicon substrate, comprising:

depositing an amorphous silicon film on a first surface of the crystalline silicon substrate, wherein the first surface of the crystalline silicon substrate is generally opposite to a second surface; and

heating the crystalline silicon substrate and the amorphous silicon film to a temperature that is sufficient to crystallize the amorphous silicon film, wherein the heating creates a temperature gradient in which the temperature at the second surface is greater than the temperature at the first surface.

2. The method of claim 1, wherein the heating comprises delivering heat to the second surface of the crystalline silicon substrate from a heating element disposed adjacent to the second surface, and the temperature at the first surface is less than the melting point of the amorphous silicon film.

3. The method of claim 1, wherein depositing the amorphous silicon film further comprises delivering a mixture of precursors comprising a silicon-containing compound into a vacuum deposition chamber in which the crystalline silicon is disposed.

4. The method of claim 3, wherein the mixture of precursors includes a dopant having opposite conductivity type from the crystalline silicon substrate.

5. The method of claim 1, further comprising forming a dielectric layer on the amorphous silicon film prior to the heating of the crystalline silicon substrate.

6. The method of claim 5, wherein the dielectric layer comprises two or more dielectric layers that each have different doping concentrations, and wherein the dielectric layer of the two or more dielectric layers that is disposed on the amorphous silicon film has a higher doping level that at least one of the other two or more dielectric layers.

7. The method of claim 1, wherein the temperature gradient is between about 2°

C. and about 10°

C.

8. The method of claim 2, wherein the heating comprises delivering heat to the second surface of the crystalline silicon substrate so that a temperature between about 750°

C. and about 1200°

C. is applied to the crystalline silicon substrate and the amorphous silicon film for between about 5 seconds and about 30 seconds.

22. The method of claim 1, wherein the temperature gradient is maintained for a period of time sufficient to crystallize at least a portion of the amorphous silicon film.

9. A method of heat treating a crystalline silicon substrate to form a p-n junction, comprising:

depositing an amorphous silicon film on a first surface of the crystalline silicon substrate, wherein the first surface of the crystalline silicon substrate is generally opposite to a second surface;

depositing a dielectric layer over the amorphous silicon film; and

heating the crystalline silicon substrate and the amorphous silicon film to a temperature that is sufficient to crystallize the amorphous silicon film, wherein the heating creates a temperature gradient between the second surface and the first surface so that a temperature of the first surface is higher than a temperature of a point within the deposited amorphous silicon film that is a distance from the first surface.

10. The method of claim 9, further comprising delivering a mixture of precursors comprising a silicon-containing compound and a phosphorous-containing compound into a vacuum deposition chamber.

11. The method of claim 9, wherein the heating comprises delivering heat to the second surface of the crystalline silicon substrate so that a temperature between about 750°

C. and about 1200°

C. is applied to the crystalline silicon substrate and the amorphous silicon film for between about 5 seconds and about 30 seconds.

12. The method of claim 9, wherein the dielectric layer is deposited in the same vacuum deposition chamber as the amorphous silicon film, and the dielectric layer is deposited prior to the heating of the crystalline silicon substrate and the amorphous silicon film.

13. The method of claim 9, wherein the temperature gradient is between about 2°

C. and about 10°

C.

14. The method of claim 9, wherein the dielectric layer comprises two or more dielectric layers that each have different doping concentrations, and wherein the dielectric layer of the two or more dielectric layers that is disposed on the amorphous silicon film has a higher doping level that at least one of the other two or more dielectric layers.

15. The method of claim 9, wherein the heating of the crystalline silicon substrate and the doped amorphous silicon film is maintained for a sufficient time to cause a higher concentration of doping atom to remain at an interface between the dielectric layer and the amorphous silicon film than the concentration of doping atom at the first surface.

20. The method of claim 9, wherein the temperature of the first surface is less than the melting point of the amorphous silicon film.

21. The method of claim 20, wherein the temperature gradient is maintained for a period of time sufficient to crystallize at least a portion of the amorphous silicon film.

16-19. -19. (canceled)