DETERMINING PERFORMANCE SENSITIVITIES OF COMPUTATIONAL UNITS

• US 20110022356A1
• Filed: 07/24/2009
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kalamatianos, John, Branover, Alexander, Nussbaum, Sebastien
• Application Number:
  US12/508,902
• Publication Number:
  US 20110022356A1
• Time in Patent Office: Days
• US Class Current: 702/182
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3006 where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3079 the data filtering being achieved by reporting only the changes of the monitored data
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Performance sensitivities to a change in performance capabilities of computational units of a computer system are determined based on measured utilization metrics for each of the computational units. In order to determine the performance sensitivities, in one approach, the computational units are operated at a first performance level, and respective first utilization metrics are determined. The computational units are then operated at a second performance level and respective second utilization metrics are determined. The sensitivity to performance capability change, e.g., a frequency change, is determined based on the respective first and second utilization metrics. The performance sensitivities of the computational units to a change in performance capability are continually updated in response to, e.g., a process context change of a computational unit or in response to a predetermined period of time elapsing since the last sensitivity to a performance capability change was determined for a computational unit.

Claims

1. A method comprising determining respective performance sensitivities to respective performance capability changes for each of a plurality of computational units of a computer system based on measured utilization metrics for each of the computational units.

2. The method as recited in claim 1 wherein the respective performance capability changes of the computational units are based on a change in at least one of clock frequency, voltage, cache size, instruction fetch rate, and number of pipelines operating.

3. The method as recited in claim 1 wherein determining the performance sensitivities further comprises:

determining respective first utilization metrics of the computational units associated with a first performance level;

determining respective second utilization metrics of the computational units associated with a second performance level; and

determining respective performance sensitivities of the computational units based on the respective first and second utilization metrics.

5. The method as recited in claim 3 further comprising identifying respective process contexts operating on respective computational units during the determination of the performance sensitivity of each of the computational units.

6. The method as recited in claim 5 further comprising storing an identification of the respective computational units, the respective process contexts, and the determined performance sensitivity for each of the computational units.

7. The method as recited in claim 3 further comprising determining the performance sensitivity for a particular one of the computational units in response to a process context change of the particular one of the computational units.

8. The method as recited in claim 3 further comprising determining the performance sensitivity for a particular one of the computational units in response to passage of a predetermined period of time since a previous sensitivity was determined for the particular one of the computational units.

9. The method as recited in claim 3 further comprising determining the first and second utilization metrics as instructions per second.

10. The method as recited in claim 1 further comprising determining the respective performance sensitivities for one computational unit at a time.

11. The method as recited in claim 1 further comprising determining the respective performance sensitivities for respective multiple computational units at a time.

12. The method as recited in claim 3 wherein the first and second performance levels are determined, at least in part, according to frequencies of one or more clock signals supplied to the computational units.

4. The method as recited in 3 further comprising determining the respective performance sensitivities as a difference between the respective first and second utilization metrics.

13. An integrated circuit comprising:

a plurality of computational units; and

control logic configured to determine respective performance sensitivities to respective performance capability changes for each of the plurality of computational units.

14. The integrated circuit as recited in claim 13 wherein the computational units comprise one or more of processing cores, a graphical processing unit and a memory controller.

15. The integrated circuit as recited in claim 13 wherein the control logic is further configured to,

apply respective clock signals at respective first frequencies to respective ones of the computational units during respective first evaluation periods and determine respective first utilization metrics associated therewith;

apply respective clock signals at respective second frequencies to the respective ones of the computational units during respective second evaluation periods and determine respective second utilization metrics associated therewith; and

determine the respective performance sensitivities for the plurality of computational units based on the respective first and second utilization metrics.

16. The integrated circuit as recited in claim 15 wherein the integrated circuit is configured to identify respective process contexts associated with respective ones of computational units during determination of respective first and second utilization metrics of the respective ones of the computational units.

17. The integrated circuit as recited in claim 16 wherein the integrated circuit is configured to store respective identifications of the respective ones of the computational units, the respective process contexts, and the respective performance sensitivities of the respective ones of the computational units.

18. The integrated circuit as recited in claim 15 wherein the integrated circuit is further configured to determine performance sensitivity for at least one of the computational units in response to a context change of the one computational unit.

19. The integrated circuit as recited in claim 15 wherein the integrated circuit is further configured to determine performance sensitivity for at least one of the computational units in response to passage of a predetermined period of time since a performance sensitivity was previously determined for the one of the computational units.

20. A computer system comprising:

a plurality of computational units; and

wherein the computer system is configured to determine respective performance sensitivities for each of the plurality of the computational units based on respective first and second performance metrics measured for each of the computational units, the respective performance sensitivities being determined for respective ones of the computational units responsive to at least one of an elapsed period of time since a previous performance sensitivity determination was made and a process context switch, for the respective ones of the computational units.

21. The computer system as recited in claim 20 further comprising storage locations storing an identification of the respective computational units, respective process contexts associated with the respective computational units, and respective performance sensitivities of the respective computational units.

22. The computer system as recited in claim 20 wherein the computational units are disposed in a single package, including one or more integrated circuits.

23. A computer readable medium encoding a computer readable description of circuits that include,

a plurality of computational units;

and

control logic configured to determine respective performance sensitivities for each of the plurality of computational units.