METHOD OF DISPATCHING AND TRANSMITTING DATA STREAMS, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

• US 20110022746A1
• Filed: 10/01/2010
• Published: 01/27/2011
• Est. Priority Date: 06/13/2008
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Chang, Ching-Wen
• Granted Patent: US 8,812,756 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.

Claims

1. A method of dispatching and transmitting data streams, for a memory storage apparatus having a non-volatile memory module and a smart card chip, the method comprising:

configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory;

receiving a read command from a host system;

determining whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determining whether the buffer memory stores the response data unit; and

transmitting the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command belongs to one of the specific logical block addresses and the buffer memory stores the response data unit.

2. The method of dispatching and transmitting data streams according to claim 1, further comprising:

transmitting a second data stream to the host system when the logical block address corresponding to the read command belongs to one of the specific logical block addresses and the buffer memory does not store the response data unit, wherein each bit of the second data stream is 0.

3. The method of dispatching and transmitting data streams according to claim 1, further comprising:

when the logical block address corresponding to the read command does not belong to any one of the specific logical block addresses, reading a third data stream corresponding to the read command from the non-volatile memory module according to the logical block address corresponding to the read command and transmitting the third data stream to the host system.

4. The method of dispatching and transmitting data streams according to claim 1, further comprising:

receiving a write command and a first data stream corresponding to the write command from the host system;

determining whether the first data stream contains a specific mark; and

when the first data stream contains the specific mark, transmitting a command data unit among the first data stream to the smart card chip and deleting the response data unit stored in the buffer memory.

5. The method of dispatching and transmitting data streams according to claim 4, further comprising:

writing the first data stream into the non-volatile memory module according to a logical block address corresponding to the write command when the first data stream does not contain the specific mark.

6. A method of dispatching and transmitting data stream, for a memory storage apparatus having a non-volatile memory module and a smart card chip, the method comprising:

configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory;

receiving a read command from a host system;

determining whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determining whether the buffer memory stores the response data unit;

determining whether the logical block address corresponding to the read command is corresponding to an access address unit when the logical block address corresponding to the read command belongs to one of the specific logical block addresses and the buffer memory stores the response data unit; and

transmitting at least a portion of the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command is corresponding to the access address unit.

7. The method of dispatching and transmitting data streams according to claim 6, further comprising:

transmitting a corresponding segment among the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command is not corresponding to the access address unit.

8. The method of dispatching and transmitting data streams according to claim 6, further comprising:

transmitting a second data stream to the host system when the logical block address corresponding to the read command belongs to one of the special logical block addresses and the buffer memory does not store the response data unit, wherein each bit of the second data stream is 0.

9. The method of dispatching and transmitting data streams according to claim 6, further comprising:

when the logical block address corresponding to the read command does not belong to any one of the special logical block addresses, reading a third data stream corresponding to the read command from the non-volatile memory module according to the logical block address corresponding to the read command and transmitting the third data stream to the host system.

10. The method of dispatching and transmitting data streams according to claim 6, further comprising:

receiving a write command and a first data stream corresponding to the write command from the host system;

determining whether the first data stream contains a specific mark; and

when the first data stream contains the specific mark, transmitting a command data unit among the first data stream to the smart card chip and deleting the response data unit stored in the buffer memory.

11. The method of dispatching and transmitting data streams according to claim 10, further comprising:

writing the first data stream into the non-volatile memory module according to a logical block address corresponding to the write command when the first data stream does not contain the specific mark.

12. A memory controller, for a memory storage apparatus having a non-volatile memory module and a smart card chip, the memory controller comprising:

a host interface, configured to couple to a host system;

a memory interface, configured to couple to the non-volatile memory module;

a buffer memory; and

a memory management circuit, coupled to the buffer memory, the host interface and the memory interface, wherein the memory management circuit is configured to;

configure a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receive a response data unit from the smart card chip and store the response data unit in the buffer memory;

receive a read command from the host system;

determine whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determine whether the buffer memory stores the response data unit; and

transmit the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command belongs to one of the special logical block addresses and the buffer memory stores the response data unit.

13. A memory controller, for a memory storage apparatus having a non-volatile memory module and a smart card chip, the memory controller comprising:

a host interface, configured to couple to a host system;

a memory interface, configured to couple to the non-volatile memory module;

a buffer memory; and

a memory management circuit, coupled to the buffer memory, the host interface and the memory interface, wherein the memory management circuit is configured to;

configure a plurality of logical block addresses, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receive a response data unit from the smart card chip and store the response data unit in the buffer memory;

receive a read command from the host system;

determine whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determine whether the buffer memory stores the response data unit;

determine whether the logical block address corresponding to the read command is corresponding to an access address unit when the logical block address corresponding to the read command belongs to one of the specific logical block addresses and the buffer memory stores the response data unit; and

transmit at least a portion of the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command is corresponding to the access address unit.

14. The memory controller according to claim 13, wherein the memory management circuit is further configured to transmit a corresponding segment among the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command is not corresponding to the access address unit.

15. The memory controller according to claim 13, wherein the memory management circuit is further configured to transmit a second data stream to the host system when the logical block address corresponding to the read command belongs to one of the special logical block addresses and the buffer memory does not store the response data unit, wherein each bit of the second data stream is 0.

16. The memory controller according to claim 13, wherein the memory management circuit is further configured to read a third data stream corresponding to the read command from the non-volatile memory module according to the logical block address corresponding to the read command and transmit the third data stream to the host system when the logical block address corresponding to the read command does not belong to one of the special logical block addresses.

17. The memory controller according to claim 13, wherein the memory management circuit is further configured to:

receive a write command and a first data stream corresponding to the write command from the host system;

determine whether the first data stream contains a specific mark; and

transmit a command data unit among the first data stream to the smart card chip and delete the response data unit stored in the buffer memory when the first data stream contains the specific mark.

18. The memory controller according to claim 17, wherein the memory management circuit is further configured to write the first data stream into the non-volatile memory module according to a logical block address corresponding to the write command when the first data stream does not contain the specific mark.

19. A memory storage apparatus, comprising:

a connector, configured to couple to a host system;

a non-volatile memory module;

a smart card chip; and

a memory controller, coupled to the connector, the non-volatile memory module and the smart card chip and having a buffer memory,

wherein the memory controller is further configured to;

configure a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receive a response data unit from the smart card chip and store the response data unit in the buffer memory;

receive a read command from the host system;

determine whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determine whether the buffer memory stores the response data unit; and

transmit the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command belongs to one of the special logical block addresses and the buffer memory stores the response data unit.

20. The memory storage apparatus according to claim 19, wherein the memory controller is further configured to transmit a second data stream to the host system when the logical block address corresponding to the read command belongs to one of the special logical block addresses and the buffer memory does not store the response data unit, wherein each bit of the second data stream is 0.

21. The memory storage apparatus according to claim 19, wherein the memory controller is further configured to read a third data stream corresponding to the read command from the non-volatile memory module according to the logical block address corresponding to the read command and transmit the third data stream to the host system when the logical block address corresponding to the read command does not belong to any one of the special logical block addresses.

22. The memory storage apparatus according to claim 19, wherein the memory controller is further configured to:

receive a write command and a first data stream corresponding to the write command from the host system;

determine whether the first data stream contains a specific mark; and

transmit a command data unit among the first data stream to the smart card chip and delete the response data unit stored in the buffer memory when the first data stream contains the specific mark.

23. The memory storage apparatus according to claim 22, wherein the memory controller is further configured to write the first data stream into the non-volatile memory module according to a logical block address corresponding to the write command when the first data stream does not contain the specific mark.

24. A memory storage apparatus, comprising:

a connector, configured to couple to a host system;

a non-volatile memory module;

a smart card chip; and

a memory controller, coupled to the connector, the non-volatile memory module and the smart card chip and having a buffer memory,

wherein the memory controller is further configured to;

configure a plurality of logical block addresses, wherein a plurality of specific logical block addresses among the logical block addresses store a specific file;

receive a response data unit from the smart card chip and store the response data unit in the buffer memory;

receive a read command from the host system;

determine whether a logical block address corresponding to the read command belongs to any one of the specific logical block addresses and determine whether the buffer memory stores the response data unit;

determine whether the logical block address corresponding to the read command is corresponding to an access address unit when the logical block address corresponding to the read command belongs to one of the specific logical block addresses and the buffer memory stores the response data unit; and

transmit at least a portion of the response data unit stored in the buffer memory to the host system when the logical block address corresponding to the read command is corresponding to the access address unit.