Fine Grained Cache Allocation

• US 20110022773A1
• Filed: 07/27/2009
• Published: 01/27/2011
• Est. Priority Date: 07/27/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Lixin, Rajamony, Ramakrishnan, Speight, William E.
• Granted Patent: US 8,543,769 B2
• Time in Patent Office: Days
• US Class Current: 711/3
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.

Claims

1. A method, in a data processing system, for fine grained cache allocation of a shared cache, the method comprising:

receiving, by a cache controller, a tag portion from an application;

setting the tag portion for a group of cache lines in a tag array of the shared cache;

responsive to an attempt to overwrite a given cache line within the group of cache lines, determining whether the given cache line is locked based on the tag portion; and

overwriting, by the cache controller, the given cache line if the cache line is not locked.

2. The method of claim 1, wherein determining whether the given cache line is locked comprises:

determining whether a lock bit associated with the tag portion associated with the given cache line is set.

3. The method of claim 1, further comprising:

receiving, by the cache controller, a mask from the application; and

storing the mask in association with the tag portion for the group of cache lines.

4. The method of claim 3, wherein determining whether the given cache line is locked comprises:

applying the mask to a real address associated with the given cache line to generate a masked real address; and

determining whether the masked real address is equal to the tag portion associated with the given cache line.

5. The method of claim 1, wherein a virtual machine monitor allocates a set of real addresses to a given virtual machine.

6. The method of claim 5, wherein the application executes within the given virtual machine and writes the tag portion to the tag array of the shared cache.

7. The method of claim 1, wherein the tag portion for the group of cache lines comprises a most significant bit portion of a tag for each cache line in the group of cache lines and wherein a least significant bit portion of the tag for each cache line in the group of cache lines comprises a private tag for a respective cache line.

8. An apparatus, in a data processing system, for fine grained cache allocation of a shared cache, the apparatus comprising:

a cache array; and

a cache controller coupled to the cache array, wherein the cache controller is configured to;

receive a tag portion from an application;

set the tag portion for a group of cache lines of the cache array in a tag array;

responsive to an attempt to overwrite a given cache line within the group of cache lines, determine whether the given cache line is locked based on the tag portion; and

overwrite the given cache line if the cache line is not locked.

9. The apparatus of claim 8, wherein determining whether the given cache line is locked comprises:

determining whether a lock bit associated with the tag portion associated with the given cache line is set.

10. The apparatus of claim 8, wherein the cache controller is further configured to:

receive a mask from the application; and

store the mask in association with the tag portion for the group of cache lines.

11. The apparatus of claim 10, wherein determining whether the given cache line is locked comprises:

applying the mask to a real address associated with the given cache line to generate a masked real address; and

determining whether the masked real address is equal to the tag portion associated with the given cache line.

12. The apparatus of claim 8, wherein a virtual machine monitor allocates a set of real addresses to a given virtual machine.

13. The apparatus of claim 12, wherein the application executes within the given virtual machine and writes the tag portion to the tag array of the shared cache.

14. The apparatus of claim 8, wherein the tag portion for the group of cache lines comprises a most significant bit portion of a tag for each cache line in the group of cache lines and wherein a least significant bit portion of the tag for each cache line in the group of cache lines comprises a private tag for a respective cache line.

15. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

receive a tag portion from an application;

set the tag portion for a group of cache lines of the cache array in a tag array;

responsive to an attempt to overwrite a given cache line within the group of cache lines, determine whether the given cache line is locked based on the tag portion; and

overwrite the given cache line if the cache line is not locked.

16. The computer program product of claim 15, wherein determining whether the given cache line is locked comprises:

determining whether a lock bit associated with the tag portion associated with the given cache line is set.

17. The computer program product of claim 15, wherein the computer readable program further causes the computing device to:

receive a mask from the application; and

store the mask in association with the tag portion for the group of cache lines.

18. The computer program product of claim 17, wherein determining whether the given cache line is locked comprises:

applying the mask to a real address associated with the given cache line to generate a masked real address; and

determining whether the masked real address is equal to the tag portion associated with the given cache line.

19. The computer program product of claim 15, wherein the computer readable program is stored in a computer readable storage medium in a data processing system and wherein the computer readable program was downloaded over a network from a remote data processing system.

20. The computer program product of claim 15, wherein the computer readable program is stored in a computer readable storage medium in a server data processing system and wherein the computer readable program is downloaded over a network to a remote data processing system for use in a computer readable storage medium with the remote system.