ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY
First Claim
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1. A method for operating a computer system including a plurality of computational units comprising:
- selectively altering performance of one or more of the computational units according to respective performance sensitivities of the computational units.
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Abstract
One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity than others of the computational units.
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Citations
21 Claims
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1. A method for operating a computer system including a plurality of computational units comprising:
selectively altering performance of one or more of the computational units according to respective performance sensitivities of the computational units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating a computer system including a plurality of processing cores comprising:
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if a predicted power margin resulting from boosting performance of a group of the processing cores is less than zero, eliminating one or more processing cores from the group, according to performance sensitivity of the one or more processing cores being lower than performance sensitivity of other of the processing cores, until the predicted power margin is greater than zero; and boosting performance of remaining processing cores in the group by increasing at least a frequency of clock signals being supplied to the remaining cores. - View Dependent Claims (12)
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13. An apparatus comprising:
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a plurality of computational units; a storage to store performance sensitivity information for the computational units; and a power allocation function configured to boost performance of one or more of the computational units according to the performance sensitivity information. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A computer readable medium encoding a computer readable description of circuits that include,
a plurality of computational units; -
a storage to store performance sensitivity information for the computational units; and a power allocation function configured to alter performance of one or more of the computational units according to the performance sensitivity information.
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Specification