THROTTLING COMPUTATIONAL UNITS ACCORDING TO PERFORMANCE SENSITIVITY

• US 20110022857A1
• Filed: 07/24/2009
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kalamatianos, John, Branover, Alexander, Nussbaum, Sebastien
• Granted Patent: US 8,443,209 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

Claims

1. A method comprising:

limiting performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability.

2. The method as recited in claim 1 further comprising limiting performance of the subset of computational units by setting a power state in which the subset may be operated.

3. The method as recited in claim 1 further comprising limiting performance of the subset of computational units by reducing a current power state of the subset to a lower power state.

4. The method as recited in claim 1 wherein the change in performance capability of each of the computational units is based on a change in at least one of clock frequency, voltage, cache size, instruction fetch rate, and number of pipelines operating.

5. The method as recited in claim 4 further comprising accessing stored performance data indicative of the sensitivities of the plurality of computational units to the change in performance capability.

6. The method as recited in claim 5 wherein the subset comprises one or more of the processing cores and the method further comprises limiting performance of the one or more of the processing cores that are least sensitive to change in performance capability according to the stored performance data.

7. The method as recited in claim 6 further comprising limiting performance of the one or more of the processing cores in response to a graphics processing unit (GPU)-bounded application being executed.

8. The method as recited in claim 1 wherein the plurality of computational units comprise a plurality of processing cores and a graphics processing unit (GPU) and responsive to a GPU-bounded application being executed, limiting performance of a first group of one or more of the processing cores forming the subset, the first group having lower performance sensitivity as compared to a second group of one or more of the processing cores, by restricting operation of the first group to a first performance state and allowing operation of the second group in a second performance state higher than the first performance state.

9. The method as recited in claim 1 wherein the plurality of computational units comprise a plurality of processing cores and responsive to a CPU-bounded application being executed, limiting performance of a first group of processing cores forming the subset, having lowest performance sensitivity, by limiting a performance state of the first group of processing cores.

10. The method as recited in claim 9 further comprising providing power margin made available by limiting performance of the first group of processing cores, to a second group of processing cores executing the CPU-bounded application.

11. The method as recited in claim 1 wherein the plurality of computational units comprise a plurality of processing cores and a graphics processing unit and responsive to a CPU-bounded application being executed, limiting performance of at least the graphics processing unit.

12. The method as recited in claim 11 further comprising limiting the performance of the graphics processing unit by limiting a graphics processing unit power state to be lower than a maximum power state.

13. The method as recited in claim 11 further comprising limiting the performance of the graphics processing unit by limiting a traffic stream of at least one of instructions and memory data to the graphics processing unit.

14. An apparatus comprising:

a plurality of processing cores;

a storage to store performance sensitivity information for the plurality of processing cores indicating performance sensitivity of each of the cores to a change in performance capability; and

wherein the apparatus is configured to limit performance of a subset of the processing cores according to the performance sensitivity information.

15. The apparatus as recited in claim 14 wherein the apparatus is further configured to limit performance of the subset of the processing cores by reducing a current power state of the subset to a lower power state.

16. The apparatus as recited in claim 14 further comprising a graphics processing unit and wherein the apparatus is configured to limit the performance of the subset of the processing cores in response to a graphics processing unit-bounded application being executed on the graphics processing unit.

17. The apparatus as recited in claim 14 wherein the apparatus is configured to limit the performance of the subset of the processing cores responsive to a CPU-bounded application being executed.

18. The apparatus as recited in claim 14 further comprising a graphics processing unit and responsive to a CPU-bounded application being executed, the apparatus limits performance of the graphics processing unit.

19. The apparatus as recited in claim 18 wherein the performance of the graphics processing unit is limited by limiting a graphics processing unit power state to be lower than a maximum graphics processing unit power state.

20. A computer readable medium encoding a computer readable description of circuits that include,

a plurality of processing cores;

a storage to store frequency sensitivity information for the plurality of processing cores indicating performance sensitivity of each of the cores to a change in frequency; and

functional circuitry configured to limit performance of a subset of the processing cores according to the frequency sensitivity information.