GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS

• US 20110023000A1
• Filed: 07/24/2009
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Mueller, Norbert, Block, Stefan, Dirks, Juergen
• Granted Patent: US 8,219,959 B2
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates.

Claims

1. A computer-implemented method of designing an integrated circuit (IC), the method comprising:

(A) defining a plurality of functional blocks for the IC, wherein at least one functional block of said plurality is an empty functional block or a functional block that is only partially rendered in circuit elements;

(B) specifying connectivity and one or more constraints for said plurality of functional blocks; and

(C) performing placement and routing processing for said plurality of functional blocks based on the specified connectivity and the specified one or more constraints to generate a layout for the IC.

2. The method of claim 1, wherein said plurality of functional blocks is a plurality of empty functional blocks.

3. The method of claim 1, wherein step (C) comprises performing the placement and routing processing based on a cost function.

4. The method of claim 3, wherein step (C) further comprises:

(C1) constructing the cost function based on one or more desired characteristics of the IC;

or

(C2) selecting the cost function from a library of available cost functions.

5. The method of claim 1, wherein step (C) comprises:

(C1) moving at least one functional block within a boundary box corresponding to the IC; and

(C2) changing at least one of shape, boundary length, and aspect ratio of at least one functional block.

6. The method of claim 1, wherein step (C) comprises:

(C1) generating a temporary floorplan, wherein a first functional block overlaps with a second functional block to produce an overlap area.

7. The method of claim 6, wherein said one or more constraints comprise a maximum permissible amount of overlap between functional blocks during the placement and routing processing.

8. The method of claim 6, wherein step (C) further comprises:

(C2) at least one of reshaping and resizing at least one of the first and second functional blocks to remove the overlap area.

9. The method of claim 8, wherein step (C2) comprises:

partitioning the overlap area into first and second portions;

subtracting the first portion from the first functional block; and

subtracting the second portion from the second functional block.

10. The method of claim 1, further comprising:

(D) at least one of reshaping and resizing at least one functional block of the plurality to create space for one or more busses that implement said connectivity; and

(E) inserting said one or more busses using the created space to generate a routed, block-structured floorplan.

11. The method of claim 10, further comprising:

(F) determining whether the routed, block-structured floorplan satisfies said one or more constraints; and

(G) if the routed block-structured floorplan satisfies said one or more constraints, then generating and saving one or more output files that describe the routed, block-structured floorplan.

12. The method of claim 11, further comprising:

(H) if the routed, block-structured floorplan does not satisfy said one or more constraints, then changing at least one parameter selected from a group of parameters consisting of (i) said one or more constraints and (ii) at least one of position, shape, boundary length, and aspect ratio for at least one functional block in the routed, block-structured floorplan; and

(I) repeating steps (C) through (G) using the changes effected in step (H).

13. The method of claim 1, wherein:

in step (A), the plurality of functional blocks is defined using a pure register-transfer-level (RTL) description without a description of netlists; and

the layout is generated based on said pure RTL description.

14. The method of claim 1, further comprising saving the layout of the IC in a machine-readable medium.

15. The method of claim 1, further comprising displaying the layout of the IC on a screen.

16. The method of claim 1, further comprising fabricating a physical embodiment of the IC based on the layout.

17. A machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements the method of claim 1.

18. A physical embodiment of the integrated circuit designed using the method of claim 1.