Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits
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Abstract
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
54 Citations
29 Claims
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1-8. -8. (canceled)
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9. A method of extracting a capacitance, the method comprising:
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reading a technology file into an extraction system; and reading a circuit layout into said extraction system; wherein said technology file includes a capacitance table; wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof. - View Dependent Claims (10, 11, 12, 13, 14, 21, 22, 23, 24, 25)
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15. A method of conducting testing and simulation, the method comprising:
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creating a technology file; processing the geometry of an integrated circuit layout; and extracting parasitic capacitance by pattern-matching a connector configuration in said technology file from a pattern in said integrated circuit layout; wherein said technology file includes a capacitance table; wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance value of an actual connector configuration in an integrated circuit (IC), said actual connector configuration comprising a contact, a via, or a combination thereof. - View Dependent Claims (16, 17, 19, 20, 26, 27, 28, 29)
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18. (canceled)
Specification