I/O MEMORY MANAGEMENT UNIT INCLUDING MULTILEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD

• US 20110023027A1
• Filed: 07/24/2009
• Published: 01/27/2011
• Est. Priority Date: 07/24/2009
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kegel, Andrew G., Hummel, Mark D.
• Granted Patent: US 8,386,745 B2
• Time in Patent Office: Days
• US Class Current: 718/1
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine

Abstract

An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables

Claims

1. An input/output (I/O) memory management unit (IOMMU) configured to control requests by an I/O device to a memory, the IOMMU comprising:

control logic configured to perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory;

wherein the translation data includes;

one or more device table entries in a device table, wherein the device table entry for a given request is selected based upon a device identifier; and

a first set of page tables including a set of guest page tables and a set of nested page tables, wherein a selected device table entry for a given request includes a pointer to the set of guest translation tables, and wherein a guest page table includes a pointer to the set of nested page tables.

2. The IOMMU as recited in claim 1, wherein the pointer to the set of guest translation tables comprises a system physical address (SPA) corresponding to an address space mapped by a virtual memory monitor (VMM) executing in on a processor of the computer system, wherein a given SPA is used to access a physical memory page in the memory.

3. The IOMMU as recited in claim 2, wherein the pointer to the set of nested page tables comprises a guest physical address (GPA) corresponding to an address space mapped by a guest operating system executing in a virtual machine (VM) on a processor of the computer system, wherein the control logic is further configured to translate the GPA to an SPA for accessing a physical memory page in the memory.

4. The IOMMU as recited in claim 2, wherein the address associated with the I/O request comprises a guest virtual address (GVA) corresponding to an address space mapped by a guest application executing in a virtual machine (VM) on a processor of the computer system, wherein the control logic is configured to translate the GVA to an SPA using the two-level guest translation.

5. The IOMMU as recited in claim 1, wherein at least some of the guest page tables include at least one entry that includes a pointer to a respective next guest page table.

6. The IOMMU as recited in claim 1, wherein a last guest page table of the set of guest page tables includes at least one entry that includes a pointer to a respective first page table of the set of nested page tables.

7. The IOMMU as recited in claim 3, wherein a last page table of the set of nested page tables includes at least one entry that includes a pointer having an address corresponding to a respective physical page in the memory.

8. The IOMMU as recited in claim 7, wherein the pointer having an address corresponding to a respective physical page in the memory comprises a GPA.

9. The IOMMU as recited in claim 8, wherein the control logic is further configured to translate the GPA pointer corresponding to a respective physical page in the memory to an SPA of the respective physical page.

10. The IOMMU as recited in claim 9, wherein the control logic is further configured to concatenate a subset of bits of the address associated with the I/O request with the SPA of the respective physical page to provide a final translation address.

11. The IOMMU as recited in claim 1, wherein the device table entry for the given request further comprises a second pointer to a second set of I/O page tables including a set of host translation page tables.

12. The IOMMU as recited in claim 11, wherein at least some of the host translation tables include entries having a pointer to a next successive host translation table, wherein each pointer comprises a system physical address (SPA) corresponding to an address space mapped by a virtual memory monitor (VMM) executing in on a processor of the computer system, wherein a given SPA is used to access a physical memory page in the memory.

28. The IOMMU as recited in claim 1, further comprising a cache memory coupled to the control logic and configured to store completed translations.

13. A system comprising:

a processor;

a memory coupled to the processor and configured to store translation data,

wherein the translation data includes;

a device table including one or more entries;

a set of page tables including a set of guest page tables and a set of nested page tables;

a least one input/output (I/O) device configured to generate a request for accessing the system memory;

an I/O memory management unit (IOMMU) coupled to the I/O device and to the memory, wherein the IOMMU is configured to perform a two-level guest translation to translate an address associated with the I/O device-generated request using the translation data;

wherein the IOMMU is configured to;

select a device table entry for a given request based upon a device identifier;

use a pointer from a selected device table entry to access the set of guest translation data structures, and

use a pointer from a guest page table to access the set of nested page tables.

14. The system as recited in claim 13, wherein the IOMMU is configured to use the device table and the set of guest page tables in a first guest translation level, and to use the set of nested page tables in a second guest translation level to obtain a final translation address.

15. The system as recited in claim 13, wherein the memory is mapped into a plurality of address spaces including a system physical address (SPA) corresponding to an address space mapped by a virtual memory monitor (VMM) executing in on the processor, a guest physical address (GPA) corresponding to an address space mapped by a guest operating system executing in a virtual machine (VM) on the processor, and a guest virtual address (GVA) corresponding to an address space mapped by a guest application executing in a virtual machine(VM) on the processor.

16. The system as recited in claim 15, wherein the pointer to the set of guest translation tables comprises an SPA, wherein a given SPA is used to access a physical memory page in the memory.

17. The system as recited in claim 15, wherein the pointer to the set of nested page tables comprises a GPA, wherein the IOMMU is further configured to translate the GPA to an SPA for accessing a physical memory page in the memory.

18. The system as recited in claim 14, wherein the address associated with the I/O request comprises a GVA, wherein the IOMMU is configured to translate the GVA to an SPA using the two-level guest translation.

19. The system as recited in claim 15, wherein the IOMMU is further configured to:

index into at least a portion of the set of guest page tables using a process identifier associated with the I/O request, and index into another portion of the set of guest page tables using the GVA associated with the I/O request.

20. The system as recited in claim 19, wherein in response to the I/O device-generated request including the process identifier, the IOMMU is configured to perform the two-level guest translation to translate the GVA associated with the I/O device-generated request.

21. The system as recited in claim 19, wherein in response to the I/O device-generated request not including the process identifier, the IOMMU is configured to perform a one-level translation to translate the address associated with the I/O device-generated request, wherein the address comprises a GPA.

22. (canceled)

23. The method as recited in claim 22, the control logic performing the two-level guest translation in response to receiving a process identifier in the I/O request.

24. The method as recited in claim 22, wherein the address received in the I/O request comprises a guest virtual address (GVA) corresponding to an address space mapped by a guest application executing in a virtual machine(VM) on a processor of the computer system.

25. The method as recited in claim 23, the control logic performing a one-level translation in response to receiving an I/O request that does not include a process identifier.

26. The method as recited in claim 25, wherein the address received in the I/O request that does not include a process identifier comprises a guest physical address (GPA) corresponding to an address space mapped by a guest operating system executing in a virtual machine(VM) on a processor of the computer system.

29. The method as recited in claim 24, further comprising the control logic storing completed translations within a cache memory.

22-1. A method for controlling input/output I/O requests to a memory of a computer system, the method comprising:

storing translation data in the system memory of a computer system, wherein the translation data includes;

one or more device table entries in a device table; and

a first set of page tables including a set of guest page tables and a set of nested page tables;

control logic performing a first translation level of a two-level guest translation on an address received in an I/O request by;

selecting a device table entry for a given request based upon a device identifier; and

using a pointer from a selected device table entry for accessing the set of guest translation tables; and

the control logic performing a second translation level of the two-level guest translation by using a pointer from a guest page table for accessing the set of nested page data structures.

27. A computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

control logic configured to perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the memory;

wherein the translation data includes;

one or more device table entries in a device table, wherein the device table entry for a given request is selected based upon a device identifier; and

a first set of page tables including a set of guest page tables and a set of nested page tables, wherein a selected device table entry for a given request includes a pointer to the set of guest translation tables, and wherein a guest page table includes a pointer to the set of nested page tables.

30. An input/output (I/O) memory management unit (IOMMU) comprising:

control logic configured to perform a multi-level hierarchical translation to translate a guest address associated with an I/O device-generated request using translation data stored in a memory, wherein the guest address corresponds to a guest virtual address space mapped by a guest application executing in a guest virtual machine on a processor;

wherein the translation data includes;

one or more device table entries in a device data structure; and

a first set of page data structures including a set of guest page data structures and a set of nested page data structures;

wherein the control logic is further configured to;

select a device data structure entry for a given request based upon a device identifier that corresponds to the I/O device that generates the request;

use a pointer from a selected device data structure entry to access the set of guest translation data structures, and

use a pointer from a guest page data structure to access the set of nested page data structures.