EXECUTING MULTIPLE THREADS IN A PROCESSOR

• US 20110023043A1
• Filed: 09/29/2010
• Published: 01/27/2011
• Est. Priority Date: 04/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lewis, Russell Lee
• Granted Patent: US 8,341,639 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Claims

1. An article of manufacture comprising a computer readable storage medium including code executed by a processor to access buffers and perform operations, the operations comprising:

setting credits in the buffers for a plurality of threads executed by the processor, wherein the credits for a thread comprise a number of credits, wherein a thread having credits can be selected for execution and wherein a thread having no credits is not selected for execution;

alternating among executing the threads having available credits;

decrementing the credits available for one of the threads to reduce the number of available credits for the thread in response to executing the thread;

setting a replenish flag for a replenish thread to indicate that the replenish thread will not execute until all the other threads have no available credits; and

initiating by the replenish thread an operation to reassign credits to the threads in response to the plurality of the threads other than the replenish thread having no available credits.

2. The article of manufacture of claim 1, wherein initiating the operation to reassign the credits comprises

alternating among executing the threads having available credit in response to the replenish thread resetting the thread credits.

3. The article of manufacture of claim 2, wherein when the threads have available credits, the replenish thread does not execute until all the threads have no available credits, and wherein the operations further comprise:

setting the replenish flag to indicate that the replenish thread is to execute to perform the operation to reassign the credits when all the threads have no available credits.

4. The article of manufacture of claim 1, wherein the thread credits are maintained in processor buffers, wherein the operations further comprise:

executing an operating system scheduler to configure the processor to execute the threads and set the thread credits.

7. The article of manufacture of claim 1, wherein the operations further comprise:

executing a pause instruction when executing one thread; and

indicating the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.

8. The article of manufacture of claim 7, wherein the operations further comprise:

initiating monitoring for an event in response to executing the pause instruction; and

indicating the thread having the paused status as not paused in response to detecting the event during the monitoring, wherein the thread whose status is changed from paused to not paused is enabled to be executed by the processor if the thread has available credits.

9. The article of manufacture of claim 8, wherein the pause instruction indicates a memory location which the thread on which the pause instruction is executed needs to access, wherein the event comprises a change to the indicated memory location.

5-6. -6. (canceled)

10. A system, comprising:

a processor;

buffers accessible to the processor;

an operating system schedule executed by the processor to perform operations, the operations comprising;

setting credits in the buffers for a plurality of threads executed by the processor wherein the credits for a thread comprise a number of credits, wherein a thread having credits can be selected for execution and wherein a thread having no credits is not selected for execution; and

code executed by the processor to perform operations, the operations comprising;

alternating among executing the threads having available credits;

decrementing the credits available for one of the threads to reduce the number of available credits for the thread in response to executing the thread;

setting a replenish flag for a replenish thread to indicate that the replenish thread will not execute until all the other threads have no available credits; and

initiating, by the replenish thread, an operation to reassign credits to the threads in response to the plurality of the threads other than the replenish thread having no available credits.

11. The system of claim 10, wherein initiating the operation to reassign the credits comprises

alternating among executing the threads having available credit in response to the replenish thread resetting the thread credits.

12. The system of claim 11, wherein when the threads have available credits, the replenish thread to does not execute until all the threads have no available credits, wherein the code is further executed by the processor to perform operations comprising:

setting the replenish flag to indicate that the replenish thread is to execute to perform the operation to reassign the credits when all the threads have no available credits.

13. The system of claim 10, wherein the buffers are included in the processor and wherein the operating system scheduler is further executed to perform operations comprising:

configuring the processor to execute the threads.

15. The system of claim 10, wherein the code is further executed by the processor to perform operations comprising:

executing a pause instruction when executing one thread; and

indicating the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.

14. (canceled)

16. A method, comprising:

setting credits for a plurality of threads executed by a processor, wherein the credits for a thread comprise a number of credits, wherein a thread having credits can be selected for execution and wherein a thread having no credits is not selected for execution;

alternating, by the processor, among executing the threads having available credits;

decrementing, by the processor, the credits available for one of the threads to reduce the number of available credits for the thread in response to executing the thread;

setting, by the processor, a replenish flag for a replenish thread to indicate that the replenish thread will not execute until all the other threads have no available credits; and

initiating an operation, by the processor, to execute a replenish thread to reassign credits to the threads in response to the plurality of the threads other than the replenish thread having no available credits.

17. The method of claim 16, wherein initiating the operation to reassign the credits comprises

alternating, by the processor, among executing the threads having available credit in response to the replenish thread resetting the thread credits.

18. The method of claim 17, wherein when the threads have available credits, the replenish thread to does not execute until all the threads have no available credits, further comprising:

setting, by the processor, the replenish flag to indicate that the replenish thread is to execute to perform the operation to reassign the credits when all the threads have no available credits.

19. The method of claim 16, wherein the thread credits are maintained in processor buffers, further comprising:

configuring, by an operating system scheduler, the processor to execute the threads and set the thread credits.

21. The method of claim 16, further comprising:

executing, by the processor, a pause instruction when executing one thread; and

indicating, by the processor, the thread in which the pause instruction is executed as paused, wherein the processor does not execute the thread indicated as paused, and wherein the operation to reassign the credits is executed in response to all the threads assigned credits either having no available credits or being in the paused state.

20. (canceled)