OPTICAL DEVICES FEATURING NONPOLAR TEXTURED SEMICONDUCTOR LAYERS

• US 20110024722A1
• Filed: 03/09/2009
• Published: 02/03/2011
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Trustees of Boston University
• Original Assignee: Trustees of Boston University
• Inventors: Abell, Joshua, Moldawer, Adam, Moustakas, Theodore D., Bhattacharyya, Anirban
• Granted Patent: US 8,592,800 B2
• Time in Patent Office: Days
• US Class Current: 257/13
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02403 Oxides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A semiconductor emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.

Claims

1. A method for fabrication of a semiconductor structure, the method comprising:

providing a substrate comprising a smooth surface having a predetermined material orientation, the substrate comprising a material selected from the group consisting of R-plane sapphire, A-plane silicon carbide, A-plane zinc oxide, A-plane gallium nitride, A-plane aluminum nitride and A-plane aluminum gallium nitride; and

depositing a first layer comprising a III-nitride material onto the smooth surface of the substrate, the first layer comprising an upper surface with a triangular texture as grown, wherein the faces of the triangles are the M-planes of the III-nitride material, and wherein the material comprises A-planes parallel to said predetermined material orientation.

2. The method of claim 1 further including depositing an upper layer onto the first layer, the upper layer comprising a III-nitride material, wherein the first layer and the upper layer comprise opposite p and n dopants, a p-n junction is formed between the first layer and the upper layer, and the upper layer replicates the texture of the first layer.

3. The method of claim 1, further including depositing one or more quantum wells on said first layer and depositing an upper layer onto the uppermost quantum well;

wherein the quantum wells comprise a III-nitride material, the upper layer comprises a III-nitride material, and the quantum wells and upper layer replicate the texture of the first layer.

4. The method of claim 1, wherein the first layer is deposited by a method comprising one of halide vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, laser ablation or a combination of these methods.

5. The method of claim 1, wherein the step of depositing said first layer provides a growth rate of at least 100μ

per hour.

6. A method for fabrication of a semiconductor device, the method comprising:

providing a substrate, the substrate comprising a material selected from the group consisting of R-plane sapphire, A-plane silicon carbide, A-plane zinc oxide, A-plane gallium nitride, A-plane aluminum nitride, and A-plane aluminum gallium nitride, wherein the substrate comprises a smooth surface having a predetermined material orientation;

depositing a first layer comprising a III-nitride material onto the smooth surface of the substrate, the first layer comprising an upper surface with a triangular texture as grown, wherein the faces of the triangles are the M-planes of the III-nitride material, and wherein the material comprises A-planes parallel to said predetermined material orientation;

depositing one or more quantum wells onto the first layer, the quantum wells comprising a III-nitride material and textured by the upper surface of the first layer; and

depositing an upper layer onto the uppermost quantum well, the upper layer comprising a III-nitride material and textured by the uppermost quantum well, wherein deposition of the first layer and the upper layer includes depositing the layers with opposite p and n dopants to comprise a p-n junction therebetween.

7. The method of claim 6, wherein the first layer is deposited by a method comprising one of halide vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, laser ablation or a combination of these methods.

8. The method of claim 6, wherein the step of depositing said first layer provides a growth rate of at least 100μ

per hour.

9. A semiconductor device comprising:

a substrate comprising a smooth surface having a predetermined material orientation, the substrate comprising a material selected from the group consisting of R-plane sapphire, A-plane silicon carbide, A-plane zinc oxide, A-plane gallium nitride, A-plane aluminum nitride, and A-plane aluminum gallium nitride;

a first layer comprising a III-nitride material having an upper surface with a triangular texture as grown, wherein the faces of the triangles are the M-planes of the III-nitride material, and wherein the material comprises A-planes parallel to said predetermined material orientation;

one or more quantum wells, each comprising a quantum well layer and a barrier layer, the quantum well layer and barrier layer each comprising a III-nitride material having a nonpolar plane oriented parallel to the M-plane of the first layer, and the one or more quantum wells overlaying the first layer; and

an upper layer comprising a III-nitride material, the upper layer overlaying the one or more quantum wells and textured by the uppermost quantum well;

wherein the upper layer is grown on the uppermost quantum well layer, and the first layer and the upper layer have opposite p and n dopants to form a p-n junction between the first layer and the upper layer.

10. The semiconductor device of claim 9, wherein the first layer is deposited by a method comprising one of halide vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, laser ablation or a combination of these methods.

11. The semiconductor device of claim 9, wherein the device has one or more of the following properties:

the textured surface of said first layer has a reflectivity of less than 1% over 325 nm to 700 nm;

the photoluminescence of the textured surface of said quantum wells is at least 90 times higher than the photoluminescence of an untextured surface of the same material;

the substrate is sapphire and the first layer is grown on the R-plane of the sapphire substrate;

the textured surface of said first layer is characterized by a series of elongated facets, each facet having approximately 120°

orientation to adjacent facets;

the entire surface of said first layer covered by said one or more quantum wells is textured;

the first layer comprises gallium nitride;

the group III-V material of said first layer and said upper layer is gallium nitride;

said one or more quantum wells comprise AlGaN, InGaN, or a combination of both; and

the device is a light emitting diode.

12. The semiconductor device of claim 9, wherein the light extraction efficiency of the device is at least 99% and the internal quantum efficiency of the device is at least 70%.

13. A semiconductor structure comprising

a substrate comprising a smooth surface having a predetermined material orientation, the substrate comprising a material selected from the group consisting of R-plane sapphire, A-plane silicon carbide, A-plane zinc oxide, A-plane gallium nitride, A-plane aluminum nitride, and A-plane aluminum gallium nitride;

a first layer comprising a III-nitride material having an upper surface with a triangular texture as grown, wherein the faces of the triangles are the M-planes of the III-nitride material, and wherein the material comprises A-planes parallel to said predetermined material orientation, the first layer overlaying the smooth surface of the substrate; and

an upper layer comprising a III-nitride material, the upper layer overlaying the first layer and textured by the first layer;

wherein the upper layer is grown on the first layer, and the first layer and the upper layer have opposite p and n dopants to form a p-n junction between the first layer and the upper layer.

14. The semiconductor device of claim 13, wherein the device has one or more of the following properties:

the textured surface of said first layer has a reflectivity of less than 1% over 325 nm to 700 nm;

the photoluminescence of the textured surface of said quantum wells is at least 90 times higher than the photoluminescence of an untextured surface of the same material;

the substrate is sapphire and the first layer is grown on the R-plane of the sapphire substrate;

the textured surface of said first layer is characterized by a series of elongated facets, each facet having approximately 120°

orientation to adjacent facets;

the entire surface of said first layer covered by said one or more quantum wells is textured;

the first layer comprises gallium nitride;

the group III-V material of said first layer and said upper layer is gallium nitride;

said one or more quantum wells comprise AlGaN, InGaN, or a combination of both; and

the device is a light emitting diode.

15. The semiconductor device of claim 13, wherein the light extraction efficiency of the device is at least 99% and the internal quantum efficiency of the device is at least 70%.

16. A template for the formation of a semiconductor device, the template comprising a nonpolar III-nitride material and formed as a layer having an upper surface and a lower surface, the upper surface having a textured as grown topology and having a nonpolar plane oriented parallel to the lower surface.

17. The template of claim 16, wherein the III-nitride material is selected from the group consisting of A-plane gallium nitride, A-plane aluminum nitride and A-plane aluminum gallium nitride.

18. The template of claim 16, further comprising a substrate bound to the lower surface of the template, the substrate comprising a material selected from the group consisting of R-plane sapphire, A-plane silicon carbide, A-plane zinc oxide, A-plane gallium nitride, A-plane aluminum nitride and A-plane aluminum gallium nitride.