SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110024751A1
• Filed: 07/29/2010
• Published: 02/03/2011
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUWABARA, Hideaki, AKIMOTO, Kengo, YAMAZAKI, Shunpei, SASAKI, Toshinari, TSUBUKU, Masashi
• Granted Patent: US 8,421,083 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

In a bottom-gate thin film transistor using the stack of the first oxide semiconductor layer and the second oxide semiconductor layer, an oxide insulating layer serving as a channel protective layer is formed over and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the insulating layer, an oxide insulating layer covering a peripheral portion (including a side surface) of the stack of the oxide semiconductor layers is formed.

Claims

1. A semiconductor device comprising:

a gate electrode layer provided over an insulating surface;

a gate insulating layer provided over the gate electrode layer;

a first oxide semiconductor layer provided over the gate insulating layer;

a second oxide semiconductor layer provided over and in contact with the first oxide semiconductor layer;

an oxide insulating layer which overlaps with a first region of the first oxide semiconductor layer and a first region of the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer; and

a source electrode layer and a drain electrode layer which are provided over the oxide insulating layer and a second region of the first oxide semiconductor layer, overlap with a second region of the second oxide semiconductor layer, and are in contact with the second oxide semiconductor layer,

wherein the first region of the first oxide semiconductor layer and the first region of the second oxide semiconductor layer are provided in a region overlapping with the gate electrode layer and in peripheries and side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the oxide insulating layer is formed using silicon oxide or aluminum oxide formed by a sputtering method.

3. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its component, or a stacked-layer film including a combination of alloy films of these elements.

4. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer are formed using indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, or zinc oxide.

5. The semiconductor device according to claim 1, further comprising:

a capacitor portion over the insulating surface; and

a capacitor wiring and a capacitor electrode overlapping with each other and included in the capacitor portion,

wherein the capacitor wiring and the capacitor electrode have a light-transmitting property.

6. The semiconductor device according to claim 1, wherein the semiconductor device is incorporated into one selected from the group consisting of an electronic book reader, a television set, a digital photo frame, a game machine, a slot machine, a portable computer, and a mobile phone.

7. The semiconductor device according to claim 1, wherein the oxide insulating layer is formed using a silicon nitride oxide or aluminum oxynitride.

8. The semiconductor device according to claim 1, wherein an average total thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is 3 nm to 30 nm.

9. The semiconductor device according to claim 1, further comprising:

a planarizing insulating layer provided over the source electrode layer and the drain electrode layer; and

a conductive layer provided over the planarizing insulating layer and connected with the gate electrode layer.

10. A semiconductor device comprising:

a gate electrode layer provided over an insulating surface;

a gate insulating layer provided over the gate electrode layer;

a first oxide semiconductor layer provided over the gate insulating layer;

a second oxide semiconductor layer provided over and in contact with the first oxide semiconductor layer;

an oxide insulating layer which overlaps with a first region of the first oxide semiconductor layer and a first region of the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer;

a source electrode layer and a drain electrode layer which are provided over the oxide insulating layer and a second region of the first oxide semiconductor layer, overlap with a second region of the second oxide semiconductor layer, and are in contact with the second oxide semiconductor layer; and

a protective insulating layer which is provided over the oxide insulating layer, the source electrode layer, the drain electrode layer, and a third region of the first oxide semiconductor layer, overlaps with a third region of the second oxide semiconductor layer, and is provided in contact with the second oxide semiconductor layer,

wherein the first region of the first oxide semiconductor layer and the first region of the second oxide semiconductor layer are provided in a region overlapping with the gate electrode layer and in peripheries and side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer.

11. The semiconductor device according to claim 10, wherein the protective insulating layer is formed using silicon nitride, aluminum oxide, or aluminum nitride formed by a sputtering method.

12. The semiconductor device according to claim 10, wherein the oxide insulating layer is formed using silicon oxide or aluminum oxide formed by a sputtering method.

13. The semiconductor device according to claim 10, wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its component, or a stacked-layer film including a combination of alloy films of these elements.

14. The semiconductor device according to claim 10, wherein the source electrode layer and the drain electrode layer are formed using indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, or zinc oxide.

15. The semiconductor device according to claim 10, further comprising:

a capacitor portion over the insulating surface; and

a capacitor wiring and a capacitor electrode overlapping with each other and included in the capacitor portion,

wherein the capacitor wiring and the capacitor electrode have a light-transmitting property.

16. The semiconductor device according to claim 10, wherein the semiconductor device is incorporated into one selected from the group consisting of an electronic book reader, a television set, a digital photo frame, a game machine, a slot machine, a portable computer, and a mobile phone.

17. The semiconductor device according to claim 10, wherein the oxide insulating layer is formed using a silicon nitride oxide or aluminum oxynitride.

18. The semiconductor device according to claim 10, wherein an average total thickness of the first oxide semiconductor layer and the second oxide semiconductor layer is 3 nm to 30 nm.

19. The semiconductor device according to claim 10, further comprising:

a planarizing insulating layer provided over the source electrode layer and the drain electrode layer; and

a conductive layer provided over the planarizing insulating layer and connected with the gate electrode layer.

20. A method for manufacturing a semiconductor device, comprising:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer over the gate insulating layer;

forming a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;

forming an oxide insulating layer which overlaps with a first region of the first oxide semiconductor layer and a first region of the second oxide semiconductor layer and is provided in contact with the second oxide semiconductor layer; and

forming a source electrode layer and a drain electrode layer which are provided over the oxide insulating layer and a second region of the first oxide semiconductor layer, overlap with a second region of the second oxide semiconductor layer, and are in contact with the second oxide semiconductor layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed without being exposed to an outside atmosphere so that intrusion of water and hydrogen into the first oxide semiconductor layer and the second oxide semiconductor layer is prevented after dehydration or dehydrogenation of the first oxide semiconductor layer and the second oxide semiconductor layer, and

the first region of the first oxide semiconductor layer and the first region of the second oxide semiconductor layer are formed in a region overlapping with the gate electrode layer and in peripheries and side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer.

21. A method for manufacturing a semiconductor device, comprising:

forming a gate electrode layer over an insulating surface;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer over the gate insulating layer;

forming a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;

forming an oxide insulating layer which overlaps with a first region of the first oxide semiconductor layer and a first region of the second oxide semiconductor layer and is provided in contact with the second oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer which are provided over the oxide insulating layer and a second region of the first oxide semiconductor layer, overlap with a second region of the second oxide semiconductor layer, and are in contact with the second oxide semiconductor layer; and

forming a protective insulating layer which is provided over the oxide insulating layer, the source electrode layer, the drain electrode layer, and a third region of the first oxide semiconductor layer, overlaps with a third region of the second oxide semiconductor layer, and is provided in contact with the second oxide semiconductor layer,

wherein the first region of the first oxide semiconductor layer and the first region of the second oxide semiconductor layer are formed in a region overlapping with the gate electrode layer and in peripheries and side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer.