SiC AVALANCHE PHOTODIODE WITH IMPROVED EDGE TERMINATION

• US 20110024768A1
• Filed: 10/16/2010
• Published: 02/03/2011
• Est. Priority Date: 03/19/2007
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Inventors: Veliadis, John V.
• Granted Patent: US 8,106,422 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 31/035281 Shape of the body
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

An avalanche photodiode semiconductor device (20) for converting an impinging photon (22) includes a base n+ doped material layer (52) formed having a window section (72) for passing the photon (22). An n− doped material layer (30) is formed on the n+ doped material layer (52) having a portion of a lower surface (74) suitably exposed. An n+ doped material layer (32) is formed on the n− doped material (30). A p+ layer (24) formed on top of the n+ doped layer (32). At least one guard ring (26) is formed in the n− doped layer (30).

Claims

1. An avalanche photodiode semiconductor device of the type for converting an impinging photon into an electrical current comprising:

a base n+ doped substrate composed of a first material and having a window section where the base n+ doped substrate has been removed for passing the photon impinging on the avalanche photodiode device;

a first n−

doped layer of said first material formed on top of the base n+ doped substrate and having a portion of a lower surface suitably exposed through the window section for receiving the photon impinging on the avalanche photodiode device;

a second upper n+ doped layer of said first material formed on the first n−

doped layer with the first n−

doped layer located between the base n+ doped substrate and the second upper n+ doped layer;

a third epitaxially grown p+ doped layer of said first material formed on top of the second upper n+ doped layer such that the second upper n+ doped layer is formed sandwiched between the first n−

doped layer and the third epitaxially grown p+ doped layer;

a pair of conductive metal contacts; and

,

at least one planar floating guard ring formed below the third epitaxially grown p+ doped layer, separated from the third epitaxially grown p+ doped layer, and doped at a level that is different than that of the third epitaxially grown p+ doped layer,

wherein a first contact is formed with the base n+ doped substrate and a second contact is formed with the third epitaxially grown p+ doped layer.

2. The invention of claim 1 wherein the at least one planar floating guard ring is formed in the first n−

doped layer and separated from the second upper n+ doped layer.

3. The invention of claim 2 wherein the first n−

doped layer, the second upper n+ doped layer, and the third epitaxially grown p+ doped layer formed into a MESA configuration.

4. The invention of claim 2 wherein sloping sidewalls are formed on the edges of the first n−

doped layer, the second upper n+ doped layer, and the third epitaxially grown p+ doped layer forming a mesa.

5. The invention of claim 2 wherein the lower portion of the first n−

doped layer surface is exposed by an etch making the lower portion of the first n−

doped layer surface antireflective.

6. The invention of claim 2 wherein the base n+ doped substrate is composed of Silicon Carbide (SiC).

7. The invention of claim 2 wherein sensitivity of the avalanche photodiode is the ultraviolet frequency range.

8. The invention of claim 2 including a passivation layer for providing electrical passivation and radiation hardness on a surface of the avalanche photodiode.

9. The invention of claim 2 wherein the photon impinges on the first n−

doped layer of the avalanche photodiode and is absorbed in the first n−

doped layer of the avalanche photodiode.

10. The invention of claim 2 wherein antireflective coatings are provided in the exposed portion of the lower surface of the first n−

doped layer.

11. The invention of claim 2 wherein solar blind coatings are provided in the exposed portion of the lower surface of the first n−

doped layer.

12. The invention of claim 2 wherein conductive metal contacts are formed from a material having a coefficient of thermal expansion that is within substantially 20% of a coefficient of thermal expansion of the avalanche photodiode'"'"'s base n+ doped substrate.

13. The invention of claim 2 wherein a portion of the first n−

doped layer extends above a top surface of the floating guard ring in the direction of the third epitaxially grown p+doped layer.

14. The invention of claim 2 wherein the avalanche photodiode has a voltage breakdown determined by the thickness and dopings of a vertical stack of constituent layers.

15. The invention of claim 1 wherein the at least one planar guard ring is formed at least partially in the second upper n+ doped layer.

16. The invention of claim 15 wherein the second upper n+ doped layer and the third epitaxially grown p+ doped layer formed into a MESA configuration.

17. The invention of claim 15 wherein sloping sidewalls are formed on the edges of the second upper n+ doped layer and the third epitaxially grown p+ doped layer forming a mesa.

18. The invention of claim 15 wherein the lower portion of the first n−

doped layer surface is exposed by an etch making the lower portion of the first n−

doped layer surface antireflective.

19. The invention of claim 15 wherein the base n+ doped substrate is composed of Silicon Carbide (SiC).

20. The invention of claim 15 wherein sensitivity of the avalanche photodiode is the ultraviolet frequency range.

21. The invention of claim 15 including a passivation layer for providing electrical passivation and radiation hardness on a surface of the avalanche photodiode.

22. The invention of claim 15 wherein the photon impinges on the first n−

doped layer of the avalanche photodiode and is absorbed in the first n−

doped layer of the avalanche photodiode.

23. The invention of claim 19 wherein antireflective coatings are provided in the exposed portion of the lower surface of the first n−

doped layer.

24. The invention of claim 19 wherein solar blind coatings are provided in the exposed portion of the lower surface of the first n−

doped layer.

25. The invention of claim 19 wherein conductive metal contacts are formed from a material having a coefficient of thermal expansion that is within substantially 20% of a coefficient of thermal expansion of the avalanche photodiode'"'"'s base n+ doped substrate.

26. The invention of claim 15 wherein a portion of the second upper n+ doped layer extends above the guard ring in the direction of the third epitaxially grown p+ doped layer.

27. The invention of claim 15 wherein the avalanche photodiode has a voltage breakdown determined by the thickness and dopings of a vertical stack of constituent layers.

28. An array structure comprising at least two avalanche photodiodes (APDs), wherein each avalanche photodiode comprises:

a base n+ doped substrate composed of a first material and having a window section where the base n+ doped substrate has been removed for passing the photon impinging on the avalanche photodiode device;

a first n−

doped layer of said first material formed on top of the base n+ doped substrate and having a portion of a lower surface suitably exposed through the window section for receiving the photon impinging on the avalanche photodiode device;

a second upper n+ doped layer of said first material formed on the first n−

doped layer with the first n−

doped layer located between the base n+ doped substrate and the second upper n+ doped layer;

a third epitaxially grown p+ doped layer of said first material formed on top of the second upper n+ doped layer such that the second upper n+ doped layer is formed sandwiched between the first n−

doped layer and the third epitaxially grown p+ doped layer; and

,

a passivation layer for providing electrical passivation and radiation hardness on a surface of the avalanche photodiode at least one planar guard ring formed in the first n−

doped layer and separated from the second upper n+ doped layer and the third epitaxially grown p+ doped layer.

29. The array structure of claim 28 wherein the base n+ doped substrate is composed of Silicon Carbide (SiC).

30. The array structure of claim 28, wherein the avalanche photodiodes have uniform breakdown voltage.

31. The array structure of claim 28, where the APDs are biased to a same reverse voltage.

32. An array structure comprising at least two avalanche photodiodes (APDs), wherein each avalanche photodiode comprises:

a base n+ doped substrate composed of a first material and having a window section where the base n+ doped substrate has been removed for passing the photon impinging on the avalanche photodiode device;

a first n−

doped layer of said first material formed on top of the base n+ doped substrate and having a portion of a lower surface suitably exposed through the window section for receiving the photon impinging on the avalanche photodiode device;

a second upper n+ doped layer of said first material formed on the first n−

doped layer with the first n−

doped layer located between the base n+ doped substrate and the second upper n+ doped layer;

a third epitaxially grown p+ doped layer of said first material formed on top of the second upper n+ doped layer such that the second upper n+ doped layer is formed sandwiched between the first n−

doped layer and the third epitaxially grown p+ doped layer; and

,

a passivation layer for providing electrical passivation and radiation hardness on a surface of the avalanche photodiode at least one planar guard ring formed partially or in its entirety in the second upper n+ doped layer and separated from the third epitaxially grown p+ doped layer.

33. The array structure of claim 32 wherein the base n+ doped substrate is composed of Silicon Carbide (SiC).

34. The array structure of claim 32, wherein the avalanche photodiodes have uniform breakdown voltage.

35. The array structure of claim 32, where the APDs are biased to a same reverse voltage.