NONVOLATILE SEMICONDUCTOR MEMORY

• US 20110024827A1
• Filed: 10/14/2010
• Published: 02/03/2011
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Fumitaka Arai, Ichiro Mizushima, Makoto Mizukami
• Original Assignee: Fumitaka Arai, Ichiro Mizushima, Makoto Mizukami
• Inventors: Mizushima, Ichiro, ARAI, Fumitaka, Mizukami, Makoto
• Granted Patent: US 8,269,267 B2
• Time in Patent Office: Days
• US Class Current: 257/326
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

Claims

1-8. -8. (canceled)

9. A nonvolatile semiconductor memory comprising:

a semiconductor substrate;

a pillar-shaped semiconductor layer which extends in a vertical direction toward the surface of the semiconductor substrate;

a plurality of memory cells which are arranged in the vertical direction on the side face of the semiconductor layer and each of which has a charge storage layer and a control gate electrode,

wherein the pillar-shaped semiconductor layer is made of a microcrystalline layer;

10. The nonvolatile semiconductor memory according to claim 9, further comprising a first select gate transistor which is arranged on the semiconductor and at the end of the plurality of memory cells on the semiconductor substrate side and which is connected to the semiconductor layer via a diffused layer, and a second select gate transistor which is arranged on the side face of the semiconductor layer and at the end of the plurality of memory cells on the opposite side of the semiconductor substrate side.

11. The nonvolatile semiconductor memory according to claim 9, wherein the grain diameter of microcrystals constituting the microcrystalline layer is less than half the smaller of the channel length and channel width of the memory cell.

12. The nonvolatile semiconductor memory according to claim 10, wherein the gate electrode of the first select gate transistor is below the control gate electrode of the memory cell via an interlayer insulating film.

13. The nonvolatile semiconductor memory according to claim 10, further comprising a source line connected to the first select gate transistor,

wherein the top surface of the source line is in a position lower than the underside of the control gate electrode of the memory cell closest to the semiconductor substrate side of the plurality of memory cells.

14. The nonvolatile semiconductor memory according to claim 9, wherein the memory cells are depletion-mode MONOS-structure transistors which have in the semiconductor layer no diffused layer serving as a source/drain region of the conductivity differing from that of the semiconductor layer.

15. The nonvolatile semiconductor memory according to claim 10, wherein the first and second select gate transistors are enhancement-mode MIS transistors.

16. The nonvolatile semiconductor memory according to claim 9, wherein each of the memory cells further has a first insulating film provided between the control gate electrode and the charge storage layer and a second insulating layer provided between the charge storage layer and the semiconductor layer.

17. The nonvolatile semiconductor memory according to claim 16, wherein the second insulating film is provided between the gate electrode of the second select gate transistor and the semiconductor layer.

18. The nonvolatile semiconductor memory according to claim 10, wherein the gate length of the second select gate transistor is greater than the control gate length of the memory cells.

19. The nonvolatile semiconductor memory according to claim 9, wherein, if the film thickness of the semiconductor layer is T and the gate length of the memory cells is L, T is greater than 1 nm and less than L×

0.8.

20. The nonvolatile semiconductor memory according to claim 9, further comprising a peripheral transistor arranged on the semiconductor substrate, wherein the peripheral transistor is an enhancement-mode MIS transistor.