MULTI-PHASE DC-TO-DC CONVERTER WITH DAISY CHAINED PULSE WIDTH MODULATION GENERATORS

• US 20110025284A1
• Filed: 08/03/2010
• Published: 02/03/2011
• Est. Priority Date: 08/03/2009
• Status: Active Grant

• Current Assignee: Monolithic Power Systems Incorporated
• Original Assignee: Monolithic Power Systems Incorporated
• Inventors: Zhou, Jinghai, Jiang, Jian, Xu, Peng
• Granted Patent: US 8,493,044 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A multi-phase DC-DC converter is disclosed. The DC-DC converter has a plurality of phases, each with a separate PWM generator for driving a totem pole of transistors. A master PWM generator operates off of a master clock signal. The remainder of the phases are slaved to the master PWM generator.

Claims

1. A circuit comprising:

an input port to receive an input signal having a sequence of pulses;

an output port;

a first functional unit to sample a master clock signal having a sequence of pulses on the input signal pulses to provide an internal clock signal having a sequence of pulses;

a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal;

a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on; and

a second functional unit to provide a sequence of pulses on the output port substantially synchronously with those master clock signal pulses immediately following a pulse in the sequence of pulses at the input port.

2. The circuit as set forth in claim 1, the first functional unit to perform the logical equivalent of a Boolean AND operation on the master clock signal and the sequence of pulses on the input port to provide the internal clock signal.

3. The circuit as set forth in claim 2, further comprising:

a clock generator to provide the master clock signal.

4. The circuit as set forth in claim 1, further comprising:

a clock generator to provide the master clock signal.

5. The circuit as set forth in claim 1, further comprising:

a master clock signal input port to receive the master clock signal.

6. A circuit comprising:

a first node having an analog supply voltage;

a second node having a high-side voltage;

a third node having a low-side voltage;

a functional unit to sample a master clock signal having a sequence of pulses on a phase of the master clock signal, the phase determined by the analog supply voltage, the high-side voltage, and the low-side voltage to provide an internal clock signal;

a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal; and

a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on.

7. The circuit as set forth in claim 6, further comprising:

a master clock signal input port to receive the master clock signal.

8. The circuit as set forth in claim 6, further comprising:

a clock generator to provide the master clock signal.

9. The circuit as set forth in claim 6, wherein the high-side voltage is equal to the analog supply voltage.

10. The circuit as set forth in claim 6, further comprising:

a resistor having a first terminal connected to the second node, and having a second terminal connected to the third node.

11. The circuit as set forth in claim 6, wherein the phase is determined by the ratio of numerator and a denominator, wherein the numerator is the difference between the analog supply voltage and the high-side voltage, and the denominator is the difference between the high-side voltage and the low-side voltage.

12. A system comprising a set of dice {D(i), i=0, 1, 2, . . . , N}, where N is an integer greater than 0,

the die D(0) comprising a clock generator to provide a master clock signal, and the die D(i) coupled to the clock generator to receive the master clock signal for each i=1, 2, . . . , N;

the die D(i) comprising an input port I(i) having a signal <

i>

, and an output port O(i), for each i=0, 1, 2, . . . , N;

wherein the input port I(i) is connected to the output port O(i−

1) for each i=1, 2, . . . , N, and the input port I(0) is connected to the output port O(N); and

the die D(i) to sample the master clock signal based upon the signal <

i>

to provide an internal clock signal C(i) and the signal <

i+1>

for each i=0, 1, 2, . . . , N−

1, and the die D(N) to sample the master clock signal based upon the signal <

N>

to provide an internal clock signal C(N) and the signal <

0>

.

13. The system as set forth in claim 12, wherein the internal clock signal C(i) is logically equivalent to the Boolean AND of the master clock signal and the signal <

i>

for each i=0, 1, 2, . . . , N.

14. The system as set forth in claim 13, the system having a startup, the master clock signal comprising a sequence of pulses, and the signal <

i>

comprising a sequence of pulses for each i=0, 1, 2, . . . , N;

where for a period time after the startup each pulse in the sequence of pulses for <

i>

begins at a master clock pulse immediately following a <

i−

1>

pulse for each i=1, 2, . . . , N and each pulse in the sequence of pulses for <

0>

begins at a master clock pulse immediately following a <

N>

pulse.

15. The system as set forth in claim 12,

the die D(i) comprising a pulse width modulation generator G(i) to provide a pulse width modulation signal PWM(i) clocked by the internal clock signal for each i=1, 2, . . . , N;

and

the die D(i) comprising a high-side power transistor TH(i) and a low-side power transistor TL(i) coupled to the pulse width modulation generator G(i) to switch on and off in response to the pulse width modulation signal PWM(i), so that the high-side power transistor TH(i) is on only if the pulse width modulation signal PWM(i) is in a first logical state, and the low-side power transistor TL(i) is on only if the pulse width modulation signal PWM(i) is in a second logical state complementary to the first logical state, such that both the high-side power transistor TH(i) and low-side power transistor TL(i) are not simultaneously on, for each i=1, 2, . . . , N.

16. The system as set forth in claim 15, further comprising:

a set of inductors {L(i) i=0, 1, 2, . . . , N} where the L(i) is coupled to the high-side power transistor TH(i) and to the low-side transistor TL(i) for each i=1, 2, . . . , N.

17. A system comprising a set of dice {D(i), i=0, 1, 2, . . . , N}, where N is an integer greater than 0,

the die D(0) comprising a clock generator to provide a master clock signal, and the die D(i) coupled to the clock generator to receive the master clock signal for each i=1, 2, . . . , N;

the die D(i) comprising a node n1(i) having an analog supply voltage, a node n2(i) having a voltage, and a node n3(i) having a voltage, for each i=0, 1, 2, . . . , N;

wherein the voltage of the node n2(0) is the analog supply voltage, and the voltage of the node n3(N) is at a ground potential;

wherein the node n3(i) is connected to the node n2(i+1) for each i=0, 1, . . . , N−

1; and

the die D(i) to sample the master clock signal on a phase P(i) of the master clock signal to provide an internal clock signal C(i), the phase P(i) determined by the analog supply voltage, the voltage of the node n2(i), and the voltage of the node n3(i) for each i=0, 1, . . . , N.

18. The system as set forth in claim 17, wherein the die D(i) comprises a resistor R(i) having a first terminal connected to the node n2(i) and a second terminal connected to the node n3(i) for each i=0, 1, . . . , N.

19. The system as set forth in claim 18, wherein the phase P(i) is determined by the ratio of a numerator and a denominator, wherein the numerator is the difference between the analog supply voltage and the voltage of the node n2(i), and the denominator is the difference between the voltage of the node n2(i) and the voltage of the node n3(i) for each i=0, 1, . . . , N.

20. The system as set forth in claim 17, wherein the die D(i) comprises a pulse width modulation generator G(i) to provide a pulse width modulation signal PWM(i) clocked by the internal clock signal for each i=1, 2, . . . , N;

and

the die D(i) comprises a high-side power transistor TH(i) and a low-side power transistor TL(i) coupled to the pulse width modulation generator G(i) to switch on and off in response to the pulse width modulation signal PWM(i), so that the high-side power transistor TH(i) is on only if the pulse width modulation signal PWM(i) is in a first logical state, and the low-side power transistor TL(i) is on only if the pulse width modulation signal PWM(i) is in a second logical state complementary to the first logical state, such that both the high-side power transistor TH(i) and low-side power transistor TL(i) are not simultaneously on, for each i=1, 2, . . . , N.

21. The system as set forth in claim 20, further comprising:

a set of inductors {L(i), i=0, 1, 2, . . . , N}, where the L(i) is coupled to the high-side power transistor TH(i) and to the low-side transistor TL(i) for each i=1, 2, . . . , N.

22. A circuit comprising:

an error input port;

a clock output port;

a resistor having a first terminal connected to the error input port, and a second terminal;

a first node connected to the second terminal of the resistor;

a first current source connected to the first node;

an operational amplifier having a first input port connected to the first node, a second input port, and an output port;

a second node connected to the second input port of the operational amplifier;

a switch coupled to the error input port, to the second node, and to the clock output port to provide a load impedance path between the error input port and the second node when a pulse is provided on the clock output port;

a capacitor connected to the second node; and

a one-shot connected to the output port of the operational amplifier to provide the pulse on the clock output port in response to the output of the operational amplifier switching from a first logical state to a second logical state, where the second logical state is complementary to the first logical state.

23. The circuit as set forth in claim 22, wherein the switch comprises an nMOSFET having a drain connected to the error input port, a source connected to the second node, and a gate connected to the clock output port.

24. The circuit as set forth in claim 22, further comprising:

a power converter having an output port;

a second operational amplifier having an input port, and an output port connected to the error input port; and

a feedback path coupling the output port of the power converter to the input port of the second operational amplifier.