MULTI-PHASE DC-TO-DC CONVERTER WITH DAISY CHAINED PULSE WIDTH MODULATION GENERATORS
First Claim
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1. A circuit comprising:
- an input port to receive an input signal having a sequence of pulses;
an output port;
a first functional unit to sample a master clock signal having a sequence of pulses on the input signal pulses to provide an internal clock signal having a sequence of pulses;
a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal;
a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on; and
a second functional unit to provide a sequence of pulses on the output port substantially synchronously with those master clock signal pulses immediately following a pulse in the sequence of pulses at the input port.
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Abstract
A multi-phase DC-DC converter is disclosed. The DC-DC converter has a plurality of phases, each with a separate PWM generator for driving a totem pole of transistors. A master PWM generator operates off of a master clock signal. The remainder of the phases are slaved to the master PWM generator.
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Citations
24 Claims
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1. A circuit comprising:
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an input port to receive an input signal having a sequence of pulses; an output port; a first functional unit to sample a master clock signal having a sequence of pulses on the input signal pulses to provide an internal clock signal having a sequence of pulses; a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal; a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on; and a second functional unit to provide a sequence of pulses on the output port substantially synchronously with those master clock signal pulses immediately following a pulse in the sequence of pulses at the input port. - View Dependent Claims (2, 3, 4, 5)
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6. A circuit comprising:
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a first node having an analog supply voltage; a second node having a high-side voltage; a third node having a low-side voltage; a functional unit to sample a master clock signal having a sequence of pulses on a phase of the master clock signal, the phase determined by the analog supply voltage, the high-side voltage, and the low-side voltage to provide an internal clock signal; a pulse width modulation generator to provide a pulse width modulation signal clocked by the internal clock signal; and a high-side power transistor and a low-side power transistor coupled to the pulse width modulation generator to switch on and off in response to the pulse width modulation signal, so that the high-side power transistor is on only if the pulse width modulation signal is in a first logical state, and the low-side power transistor is on only if the pulse width modulation signal is in a second logical state complementary to the first logical state, such that both the high-side and low-side power transistors are not simultaneously on. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A system comprising a set of dice {D(i), i=0, 1, 2, . . . , N}, where N is an integer greater than 0,
the die D(0) comprising a clock generator to provide a master clock signal, and the die D(i) coupled to the clock generator to receive the master clock signal for each i=1, 2, . . . , N; -
the die D(i) comprising an input port I(i) having a signal <
i>
, and an output port O(i), for each i=0, 1, 2, . . . , N;
wherein the input port I(i) is connected to the output port O(i−
1) for each i=1, 2, . . . , N, and the input port I(0) is connected to the output port O(N); andthe die D(i) to sample the master clock signal based upon the signal <
i>
to provide an internal clock signal C(i) and the signal <
i+1>
for each i=0, 1, 2, . . . , N−
1, and the die D(N) to sample the master clock signal based upon the signal <
N>
to provide an internal clock signal C(N) and the signal <
0>
. - View Dependent Claims (13, 14, 15, 16)
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17. A system comprising a set of dice {D(i), i=0, 1, 2, . . . , N}, where N is an integer greater than 0,
the die D(0) comprising a clock generator to provide a master clock signal, and the die D(i) coupled to the clock generator to receive the master clock signal for each i=1, 2, . . . , N; -
the die D(i) comprising a node n1(i) having an analog supply voltage, a node n2(i) having a voltage, and a node n3(i) having a voltage, for each i=0, 1, 2, . . . , N;
wherein the voltage of the node n2(0) is the analog supply voltage, and the voltage of the node n3(N) is at a ground potential;
wherein the node n3(i) is connected to the node n2(i+1) for each i=0, 1, . . . , N−
1; andthe die D(i) to sample the master clock signal on a phase P(i) of the master clock signal to provide an internal clock signal C(i), the phase P(i) determined by the analog supply voltage, the voltage of the node n2(i), and the voltage of the node n3(i) for each i=0, 1, . . . , N. - View Dependent Claims (18, 19, 20, 21)
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22. A circuit comprising:
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an error input port; a clock output port; a resistor having a first terminal connected to the error input port, and a second terminal; a first node connected to the second terminal of the resistor; a first current source connected to the first node; an operational amplifier having a first input port connected to the first node, a second input port, and an output port; a second node connected to the second input port of the operational amplifier; a switch coupled to the error input port, to the second node, and to the clock output port to provide a load impedance path between the error input port and the second node when a pulse is provided on the clock output port; a capacitor connected to the second node; and a one-shot connected to the output port of the operational amplifier to provide the pulse on the clock output port in response to the output of the operational amplifier switching from a first logical state to a second logical state, where the second logical state is complementary to the first logical state. - View Dependent Claims (23, 24)
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Specification