CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS
First Claim
Patent Images
1. An electronic circuit comprising:
- a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has a first nominal threshold voltage; and
a second transistor of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has a second nominal threshold voltage;
wherein the first nominal threshold voltage is different from the second nominal threshold voltage.
1 Assignment
0 Petitions
Accused Products
Abstract
CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.
16 Citations
26 Claims
-
1. An electronic circuit comprising:
-
a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has a first nominal threshold voltage; and a second transistor of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has a second nominal threshold voltage; wherein the first nominal threshold voltage is different from the second nominal threshold voltage. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A power switch comprising:
-
a first transistor having a source terminal coupled to a voltage source and a drain terminal coupled to a local voltage node, the first transistor having a first nominal threshold voltage; and a second transistor having a source terminal coupled to the voltage source and a drain terminal coupled to the local voltage node, the second transistor having a second nominal threshold voltage different from the first nominal threshold voltage; wherein a gate terminal of both the first and second transistors is coupled to receive a signal, and wherein the signal, when asserted, causes the first and second transistors to be deactivated. - View Dependent Claims (8, 9, 10, 11)
-
-
12. A logic gate comprising:
-
a plurality of p-type metal oxide semiconductor (PMOS) transistors including a first PMOS transistor configured to activate based on a first gate-source voltage and a second PMOS transistor configured to activate responsive to a second gate-source voltage different from the first gate-source voltage; and a plurality of n-type metal oxide semiconductor (NMOS) transistors including a first NMOS transistor configured to activate based on a third gate-source voltage and a second NMOS transistor configured to activate responsive to a fourth gate-source voltage different from the third gate-source voltage. - View Dependent Claims (13, 14, 15)
-
-
16. An integrated circuit comprising:
a plurality of logic gates, wherein the power switch circuit and each of the plurality of logic gates includes a first plurality of p-type metal oxide semiconductor (PMOS) transistors, a second plurality of PMOS transistors, a first plurality of n-type metal oxide semiconductor (NMOS) transistors, and a second plurality of NMOS transistors, wherein; each of the PMOS transistors of the first plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a first nominal threshold voltage; each of the PMOS transistors of the second plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a second nominal threshold voltage; each of the NMOS transistors of the first plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a third nominal threshold voltage; and each of the NMOS transistors of the second plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a fourth nominal threshold voltage. - View Dependent Claims (17, 18, 19, 20)
-
21. An integrated circuit
a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has one or more first nominal properties; -
a second transistor, wherein the second transistor is of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has one or more second nominal properties; wherein the first nominal component property is different from the second nominal component property. - View Dependent Claims (22, 23, 24, 25, 26)
-
Specification