SWITCHES WITH BIAS RESISTORS FOR EVEN VOLTAGE DISTRIBUTION

• US 20110025408A1
• Filed: 11/09/2009
• Published: 02/03/2011
• Est. Priority Date: 07/30/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Dunworth, Jeremy D., Cassia, Marco
• Granted Patent: US 8,395,435 B2
• Time in Patent Office: Days
• US Class Current: 327/535
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.

Claims

1. An apparatus comprising:

a plurality of transistors coupled in a stack and having a first voltage applied to a first transistor in the stack and further having a second voltage applied to bulk nodes of the plurality of transistors, the second voltage being lower than the first voltage; and

at least one resistor coupled to at least one intermediate node in the stack to maintain matching bias conditions for the plurality of transistors when turned off, each intermediate node corresponding to a connection between a source of one transistor and a drain of another transistor in the stack.

2. The apparatus of claim 1, the at least one resistor comprises one resistor for each transistor in the stack, each resistor is coupled between the source and drain of an associated transistor.

3. The apparatus of claim 1, each of the at least one resistor is coupled between a respective intermediate node and the first voltage.

4. The apparatus of claim 1, further comprising:

a plurality of bulk bias resistors for the plurality of transistors, one bulk bias resistor for each transistor, each bulk bias resistor is coupled between a bulk node of an associated transistor and the second voltage.

5. The apparatus of claim 1, the at least one resistor maintains the source of each of the plurality of transistors at the first voltage to maintain matching bias conditions for the plurality of transistors when turned off.

6. The apparatus of claim 1, the at least one resistor maintains zero drain-to-source voltage for each of the plurality of transistors to maintain matching bias conditions for the plurality of transistors when turned off.

7. The apparatus of claim 1, the first voltage is zero Volts, the second voltage is a negative voltage, and each of the plurality of transistors has a negative source-to-bulk voltage.

8. The apparatus of claim 1, the plurality of transistors form a switch receiving an input radio frequency (RF) signal, and the first voltage is determined by a direct current (DC) component of the input RF signal.

9. The apparatus of claim 1, the at least one resistor is implemented with poly-silicon.

10. The apparatus of claim 1, the at least one resistor has a value larger than an impedance of each transistor when turned off.

11. The apparatus of claim 1, the plurality of transistors comprises metal oxide semiconductor (MOS) transistors.

12. An integrated circuit comprising:

a plurality of metal oxide semiconductor (MOS) transistors coupled in a stack and having a first voltage applied to a first MOS transistor in the stack and further having a second voltage applied to bulk nodes of the plurality of MOS transistors, the second voltage being lower than the first voltage; and

at least one resistor coupled to at least one intermediate node in the stack to maintain matching bias conditions for the plurality of MOS transistors when turned off, each intermediate node corresponding to a connection between a source of one MOS transistor and a drain of another MOS transistor in the stack.

13. The integrated circuit of claim 12, the at least one resistor comprises one resistor for each MOS transistor in the stack, each resistor is coupled between the source and drain of an associated MOS transistor.

14. The integrated circuit of claim 12, each of the at least one resistor is coupled between a respective intermediate node and the first voltage.

15. The integrated circuit of claim 12, further comprising:

a plurality of bulk bias resistors for the plurality of MOS transistors, one bulk bias resistor for each MOS transistor, each bulk bias resistor is coupled between a bulk node of an associated MOS transistor and the second voltage.

16. An apparatus comprising:

a module comprising multiple switches to implement multiple signal paths, the module receiving a radio frequency (RF) signal and routing the RF signal via one of the multiple signal paths, each of the multiple switches comprising

a plurality of transistors coupled in a stack and having a first voltage applied to a first transistor in the stack and further having a second voltage applied to bulk nodes of the plurality of transistors, the second voltage being lower than the first voltage, and

at least one resistor coupled to at least one intermediate node in the stack to maintain matching bias conditions for the plurality of transistors when turned off.

17. The apparatus of claim 16, the module is a switchplexer coupled to an antenna.

18. The apparatus of claim 16, the module is a power amplifier (PA) module further comprising at least one power amplifier for amplifying the RF signal.

19. A method comprising:

applying a first voltage to a first transistor among a plurality of transistors coupled in a stack;

applying a second voltage to bulk nodes of the plurality of transistors, the second voltage being lower than the first voltage; and

maintaining matching bias conditions for the plurality of transistors when turned off.

20. The method of claim 19, the maintaining matching bias conditions comprising maintaining zero drain-to-source voltage for each of the plurality of transistors with a resistor coupled between the source and drain of each transistor.

21. The method of claim 19, the maintaining matching bias conditions comprising maintaining a source of each of the plurality of transistors at the first voltage with a resistor coupled between each intermediate node in the stack and the first voltage.

22. An apparatus comprising:

means for applying a first voltage to a first transistor among a plurality of transistors coupled in a stack;

means for applying a second voltage to bulk nodes of the plurality of transistors, the second voltage being lower than the first voltage; and

means for maintaining matching bias conditions for the plurality of transistors when turned off.

23. The apparatus of claim 22, the means for maintaining matching bias conditions comprising means for maintaining zero drain-to-source voltage for each of the plurality of transistors with a resistor coupled between the source and drain of each transistor.

24. The apparatus of claim 22, the means for maintaining matching bias conditions comprising means for maintaining a source of each of the plurality of transistors at the first voltage to maintain matching bias conditions for the plurality of transistors when turned off.