POWER AMPLIFIER BIAS CURRENT MONITOR AND CONTROL MECHANISM

• US 20110025422A1
• Filed: 02/11/2010
• Published: 02/03/2011
• Est. Priority Date: 07/30/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Marra, Thomas D., Hadjichristos, Aristotele, Pietcher, Nathan M.
• Granted Patent: US 9,166,533 B2
• Time in Patent Office: Days
• US Class Current: 330/296
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Claims

1. An apparatus comprising:

an amplifier comprising a first transistor; and

a bias circuit comprising a second transistor coupled to the first transistor in the amplifier, the first and second transistors form a current mirror, the bias circuit generates a bias voltage for the first and second transistors to obtain a target bias current for the first transistor.

2. The apparatus of claim 1, the bias circuit further comprises a current source coupled to the second transistor, the bias circuit generates the bias voltage to obtain a target current from the current source, and the target current from the current source is determined based on the target bias current for the first transistor.

3. The apparatus of claim 1, the amplifier is a power amplifier, and the first transistor is an N-channel metal oxide semiconductor (NMOS) transistor.

4. An apparatus comprising:

an amplifier comprising a transistor coupled to an inductor;

a sensing circuit coupled to the inductor and to measure a voltage across the inductor; and

a bias circuit coupled to the transistor and to generate a bias voltage for the transistor based on the measured voltage across the inductor to obtain a target bias current for the transistor.

5. The apparatus of claim 4, further comprising:

an analog-to-digital converter (ADC) to digitize the measured voltage and provide a digitized voltage; and

a processor to receive the digitized voltage and generate a control for the bias circuit based on the digitized voltage.

6. The apparatus of claim 5, the processor determines a measured bias current for the transistor based on the digitized voltage and a resistor value for the inductor and generates the control for the bias circuit based on the measured bias current and the target bias current.

7. The apparatus of claim 6, the resistor value for the inductor is determined by applying a known current through the inductor and measuring the voltage across the inductor.

8. The apparatus of claim 6, the resistor value for the inductor is determined based on integrated circuit (IC) conditions observed by the amplifier.

9. An apparatus comprising:

an amplifier comprising first and second transistors coupled in a stack;

a sensing circuit coupled to the second transistor in the amplifier and to measure a gate-to-source voltage, Vgs, of the second transistor; and

a bias circuit coupled to at least one transistor among the first and second transistors and to generate at least one bias voltage for the at least one transistor based on the measured Vgs voltage of the second transistor to obtain a target bias current for the first and second transistors.

10. The apparatus of claim 9, the first transistor is a lower transistor in the stack and is coupled to circuit ground, and the second transistor is an upper transistor in the stack.

11. The apparatus of claim 9, further comprising:

an analog-to-digital converter (ADC) to digitize the measured Vgs voltage and provide a digitized voltage; and

a processor to receive the digitized voltage and generate a control for the bias circuit based on the digitized voltage.

12. The apparatus of claim 11, the processor determines a target Vgs voltage corresponding to the target bias current and generates the control for the bias circuit based on the measured Vgs voltage and the target Vgs voltage.

13. The apparatus of claim 11, further comprising:

a look-up table to store bias current versus Vgs voltage for the second transistor, the processor obtains a measured bias current for the measured Vgs voltage from the look-up table and generates the control for the bias circuit based on the measured bias current and the target bias current.

14. The apparatus of claim 9, further comprising:

a replica circuit comprising third and fourth transistors coupled in a stack and replicating the first and second transistors in the amplifier; and

a second sensing circuit coupled to the fourth transistor in the replica circuit and to measure a Vgs voltage of the fourth transistor, and

the bias circuit generates the at least one bias voltage for the at least one transistor in the amplifier based on the measured Vgs voltage of the second transistor and the measured Vgs voltage of the fourth transistor.

15. The apparatus of claim 14, the first and third transistors receive a first bias voltage, and the second and fourth transistors receive a second bias voltage.

16. The apparatus of claim 15, further comprising:

an analog-to-digital converter (ADC) to digitize the measured Vgs voltage of the second transistor and provide a first digitized voltage and to digitize the measured Vgs voltage of the fourth transistor and provide a second digitized voltage; and

a processor to receive the first and second digitized voltages and generate a control for the bias circuit based on the first and second digitized voltages.

17. The apparatus of claim 16, the processor obtains the second digitized voltage for the measured Vgs voltage of the fourth transistor with the first and second bias voltages having nominal values and generates the control for the bias circuit to cause the measured Vgs voltage of the second transistor to match the measured Vgs voltage of the fourth transistor.

18. An apparatus comprising:

an amplifier comprising at least one transistor;

a replica circuit comprising at least one transistor replicating the at least one transistor in the amplifier; and

a feedback circuit coupled to the amplifier and the replica circuit and to sense a first voltage in the amplifier, to sense a second voltage in the replica circuit, and to generate a bias voltage for the amplifier based on the first and second voltages.

19. The apparatus of claim 20, the feedback circuit comprising

a filter to receive and filter the first voltage and provide a third voltage, and

a sensing circuit to receive the second and third voltages and generate the bias voltage for the gate of the first transistor.

20. The apparatus of claim 18, the amplifier comprising first and second transistors coupled in a stack, the replica circuit comprising third and fourth transistors coupled in a stack, the first voltage is a drain voltage of the first transistor, the second voltage is a drain voltage of the third transistor, and the bias voltage is applied to a gate of the first transistor.

21. The apparatus of claim 20, the second and fourth transistors receive a second bias voltage, the third transistor receives a third bias voltage, and the second and third bias voltages provide a target bias current for the third and fourth transistors in the replica circuit.

22. An apparatus comprising:

an amplifier to amplify an input signal and provide an output signal;

a switched mode power supply (SMPS) coupled to the amplifier and to receive a first supply voltage and provide a second supply voltage to the amplifier; and

a bias circuit coupled to the amplifier and to generate a bias voltage for the amplifier to obtain a target bias current for the amplifier.

23. The apparatus of claim 22, the bias circuit receives a control determined based on a measured bias current for the amplifier with the SMPS disabled and generates the bias voltage for the amplifier based on the control.

24. The apparatus of claim 22, further comprising:

a resistor operatively coupled to the amplifier and to provide a bias current for the amplifier when the SMPS is disabled;

a sensing circuit coupled to the resistor and to measure a voltage across the resistor, and

the bias circuit receives a control determined based on the measured voltage across the resistor and generates the bias voltage for the amplifier based on the control.

25. The apparatus of claim 24, further comprising:

an analog-to-digital converter (ADC) to digitize the measured voltage across the resistor and provide a digitized voltage; and

a processor to receive the digitized voltage and generate the control for the bias circuit based on the digitized voltage.

26. The apparatus of claim 25, the processor determines a measured bias current for the amplifier based on the digitized voltage and a known value of the resistor and generates the control for the bias circuit based on the measured bias current and the target bias current.

27. The apparatus of claim 22, the amplifier comprises a first transistor, the apparatus further comprising:

a second transistor coupled to the first transistor in the amplifier via at least one switch, the first and second transistors form a current mirror when the at least one switch is closed; and

a sensing circuit to coupled to the second transistor and to measure a current through the second transistor, and

the bias circuit receives a control determined based on the measured current through the second transistor and the target bias current for the amplifier.

28. The apparatus of claim 27, further comprising:

an analog-to-digital converter (ADC) to digitize a sensed voltage from the sensing circuit, the sensed voltage is indicative of the measured current through the second transistor; and

a processor to receive the digitized voltage from the ADC and generate the control for the bias circuit based on the digitized voltage.

29. The apparatus of claim 28, the processor determines a measured bias current for the amplifier based on the digitized voltage and generates the control for the bias circuit based on the measured bias current and the target bias current.

30. A method of adjusting bias current, comprising:

obtaining a measurement of a voltage across an inductor coupled to at least one transistor in an amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage, Vgs, of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply (SMPS) disabled; and

generating at least one bias voltage for the at least one transistor in the amplifier based on the measurement to obtain a target bias current for the amplifier.

31. The method of claim 30, the generating the at least one bias voltage comprising

determining a measured bias current for the amplifier based on the current through the current mirror formed with one of the at least one transistor in the amplifier, and

generating the at least one bias voltage based on the measured bias current and the target bias current for the amplifier.

32. The method of claim 30, the generating the at least one bias voltage comprising

digitizing the voltage across the inductor to obtain a digitized voltage,

determining a measured bias current for the amplifier based on the digitized voltage and a resistor value for the inductor, and

generating the at least one bias voltage based on the measured bias current and the target bias current for the amplifier.

33. The method of claim 30, the generating the at least one bias voltage comprising

determining a measured bias current for the amplifier based on the Vgs voltage of one of the at least one transistor in the amplifier, and

generating the at least one bias voltage based on the measured bias current and the target bias current for the amplifier.

34. The method of claim 30, the generating the at least one bias voltage comprising generating the at least one bias voltage based on the Vgs voltage of one of the at least one transistor in the amplifier and a target Vgs voltage.

35. The method of claim 30, the generating the at least one bias voltage comprising

obtaining a second measurement of a Vgs voltage of one of at least one transistor in the replica circuit, and

generating the at least one bias voltage for the at least one transistor in the amplifier based further on the second measurement to obtain the target bias current for the amplifier.

36. The method of claim 30, the generating the at least one bias voltage comprising

sensing a voltage in the amplifier, and

generating a bias voltage for the amplifier based on the voltage in the replica circuit and the voltage in the amplifier using a feedback loop.

37. The method of claim 30, the obtaining the measurement comprising

measuring a voltage across a resistor coupled to the amplifier with the SMPS disabled, and

determining the current applied to the amplifier based on the measured voltage.

38. The method of claim 30, the obtaining the measurement comprising

measuring a current through a current mirror formed with one of the at least one transistor in the amplifier, and

determining the current applied to the amplifier based on the measured current through the current mirror.

39. An apparatus for bias adjustment, comprising:

means for obtaining a measurement of a voltage across an inductor coupled to at least one transistor in an amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage, Vgs, of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply (SMPS) disabled; and

means for generating at least one bias voltage for the at least one transistor in the amplifier based on the measurement to obtain a target bias current for the amplifier.