Level Shifters and Display Devices Using the Same

• US 20110025734A1
• Filed: 07/16/2010
• Published: 02/03/2011
• Est. Priority Date: 07/29/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Woo-Chol, Choi, Jae-bum
• Granted Patent: US 8,471,803 B2
• Time in Patent Office: Days
• US Class Current: 345/698
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

Provided are a level shifter and a display device including the level shifter. The level shifter includes: a first circuit that blocks a supply of a source voltage to a first node while a signal input to an input terminal is maintained at a logic high level, and that supplies the source voltage to the first node while the signal input to the input terminal is transitioned from a logic high level to a logic low level; a second circuit that supplies the source voltage to the first node only when a voltage of an output terminal is maintained at a logic low level; a first inverter that reverses a logical level of the signal input to the input terminal by using the voltage supplied from the first node and outputs the signal to a second node; and a second inverter that reverses the logical level of the signal input to the second node by using the source voltage and outputs the signal to the output terminal.

Claims

1. A level shifter comprising:

a first circuit that is configured to block a supply of a source voltage to a first node when a signal input to an input terminal is maintained at a logic high level, and to supply the source voltage to the first node when the signal input to the input terminal transitions from a logic high level to a logic low level;

a second circuit that is configured to supply the source voltage to the first node only when a voltage of an output terminal is maintained at a logic low level;

a first inverter that uses the voltage supplied from the first node to generate a first output signal by reversing a logical level of the signal input to the input terminal and outputs the first output signal to a second node; and

a second inverter that uses the source voltage to generate a second output signal by reversing the logical level of the first output signal that is output to the second node and outputs the second output signal to the output terminal.

2. The level shifter of claim 1, wherein the first circuit comprises:

a first P-channel transistor comprising a source terminal connected to a source voltage terminal, a drain terminal connected to a third node, and a gate terminal connected to a terminal that is maintained at a logic low state;

a second P-channel transistor comprising a source terminal connected to the source voltage terminal, a drain terminal connected to the first node, and a gate terminal connected to the third node; and

a first capacitor comprising a first terminal connected to the input terminal, and a second terminal connected to the third node.

3. The level shifter of claim 2, wherein the terminal that is maintained at a logic low state comprises a ground terminal.

4. The level shifter of claim 1, wherein the second circuit comprises a third P-channel transistor comprising a source terminal connected to the source voltage terminal, a drain terminal connected to the first node, and a gate terminal connected to the output terminal.

5. The level shifter of claim 2, further comprising a second capacitor comprising a first terminal connected to the source voltage terminal and a second terminal connected to the first node.

6. The level shifter of claim 5, wherein the first capacitor and the second capacitor comprise metal-oxide-semiconductor (MOS) devices.

7. The level shifter of claim 1, wherein the first inverter comprises:

a fifth P-channel transistor comprising a gate terminal connected to the input terminal, a source terminal connected to the first node, and a drain terminal connected to the second node; and

a first N-channel transistor comprising a gate terminal connected to the input terminal, a drain terminal connected to the second node, and a source terminal to the ground terminal.

8. The level shifter of claim 1, wherein the second inverter comprises:

a fourth P-channel transistor comprising a gate terminal connected to the second node, a source terminal connected to the source voltage terminal, and a drain terminal connected to the output terminal; and

a second N-channel transistor comprising a gate terminal connected to the second node, a drain terminal connected to the output terminal, and a source terminal connected to the ground terminal.

16. The level shifter of claim 3, wherein the second circuit comprises a third P-channel transistor comprising a source terminal connected to the source voltage terminal, a drain terminal connected to the first node, and a gate terminal connected to the output terminal.

17. The level shifter of claim 16, further comprising a second capacitor comprising a first terminal connected to the source voltage terminal and a second terminal connected to the first node.

18. The level shifter of claim 17, wherein the first inverter comprises:

a fifth P-channel transistor comprising a gate terminal connected to the input terminal, a source terminal connected to the first node, and a drain terminal connected to the second node; and

a first N-channel transistor comprising a gate terminal connected to the input terminal, a drain terminal connected to the second node, and a source terminal to the ground terminal.

19. The level shifter of claim 18, wherein the second inverter comprises:

a fourth P-channel transistor comprising a gate terminal connected to the second node, a source terminal connected to the source voltage terminal, and a drain terminal connected to the output terminal; and

a second N-channel transistor comprising a gate terminal connected to the second node, a drain terminal connected to the output terminal, and a source terminal connected to the ground terminal.

9. A display device comprising:

a panel comprising a plurality of pixel arrays and a first driving circuit for driving the plurality of pixel arrays;

a second driving circuit generating a signal for driving the panel; and

a level shifter that is configured to convert a voltage level of the signal generated by the second driving circuit to a voltage level appropriate for driving the first driving circuit,

wherein the level shifter comprises;

a first circuit that is configured to block a supply of a source voltage to a first node when a signal input to of an input terminal is maintained at a logic high level and to supply a source voltage to the first node when the signal input to the input terminal is transitions from a logic high level to a logic low level;

a second circuit that is configured to supply the source voltage to the first node only when a voltage of an output terminal is maintained at a logic low level;

a first inverter that uses the voltage supplied from the first node to generate a first output signal by reversing a logical level of the signal input to the input terminal and outputs the first output signal to a second node; and

a second inverter that uses the source voltage to generate a second output signal by reversing the logical level of the first output signal that is output to the second node and outputs the second output signal to the output terminal.

10. The display device of claim 9, wherein the first circuit comprises:

a first P-channel transistor comprising a source terminal connected to a source voltage terminal, a drain terminal connected to a third node, and a gate terminal connected to a terminal that is maintained at a logic low state;

a second P-channel transistor comprising a source terminal connected to the source voltage terminal, a drain terminal to the first node, and a gate terminal to the third node; and

a first capacitor comprising a first terminal connected to the input terminal, and a second terminal connected to the third node.

11. An electronic circuit, comprising:

an input terminal;

an output terminal;

a first inverter comprising a first P-channel transistor having a source connected to a first node and a drain connected to a second node and a gate connected to the input terminal and a first N-channel transistor having a drain connected to the second node, a source connected to ground and a gate connected to the input terminal;

a second inverter comprising a third P-channel transistor having a source connected to a source voltage terminal and a drain connected to the output terminal and a gate connected to the second node and a fourth N-channel transistor having a drain connected to the output terminal, a source connected to ground and a gate connected to the second node;

a fifth transistor having a source connected to the source voltage terminal and a drain connected to the first node; and

a sixth transistor having a source connected to the source voltage terminal and a drain connected to the first node.

12. The electronic circuit of claim 11, wherein the fifth transistor comprises an N-channel transistor having a gate that is connected to the source voltage terminal and wherein the sixth transistor comprises a P-channel transistor having a gate connected to the output terminal.

13. The electronic circuit of claim 11, wherein the fifth transistor comprises a P-channel transistor having a gate that is connected to a third node and wherein the sixth transistor comprises a P-channel transistor having a gate connected to the output terminal, the electronic circuit further comprising a seventh transistor having a source connected to the source voltage terminal, a drain connected to the third node.

14. The electronic circuit of claim 13, further comprising a first capacitor coupled between the input terminal and the third node.

15. The electronic circuit of claim 14, further comprising a second capacitor coupled between the source voltage terminal and the first node.