SYSTEM-IN PACKAGES

• US 20110026232A1
• Filed: 07/22/2010
• Published: 02/03/2011
• Est. Priority Date: 07/30/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Granted Patent: US 8,503,186 B2
• Time in Patent Office: Days
• US Class Current: 361/760
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Claims

1. A system-in package comprising:

a carrier;

a first chip over said carrier, wherein said first chip comprises a first semiconductor substrate having a thickness between 1 and 50 micrometers, a first metal layer under a bottom surface of said first semiconductor substrate, and a dielectric layer under said bottom surface of said first semiconductor substrate and over said first metal layer;

a second chip over said carrier, wherein said second chip comprises a second semiconductor substrate, wherein said second semiconductor substrate has a top surface substantially coplanar with a top surface of said first semiconductor substrate, wherein said second chip is separated from said first chip;

a gap filling material disposed in a gap between said first chip and said second chip;

a first metal plug in said first chip, wherein said first metal plug passes through said first semiconductor substrate and said dielectric layer and contacts said first metal layer;

a first insulating material enclosing said first metal plug, wherein said first insulating material is enclosed by said first semiconductor substrate;

a first dielectric structure on said top surface of said first semiconductor substrate, on said top surface of said second semiconductor substrate, and on said gap filling material;

a first metal interconnect in said first dielectric structure and over said first chip, wherein said first metal interconnect is connected to said first metal plug;

a third chip over said first dielectric structure and over said first metal interconnect, wherein said third chip comprises a third semiconductor substrate having a thickness between 1 and 50 micrometers;

a second metal plug in said third chip, wherein said second metal plug passes through said third chip and contacts said first metal interconnect;

a second insulating material enclosing said second metal plug, wherein said second insulating material is enclosed by said third semiconductor substrate;

a second dielectric structure on a top surface of said third semiconductor substrate; and

a second metal interconnect in said second dielectric structure and over said third chip, wherein said second metal interconnect is connected to said second metal plug.

2. The system-in package of claim 1, wherein said carrier comprises one of a silicon substrate, a glass substrate, a ceramic substrate, a metal substrate, and an organic polymer substrate.

3. The system-in package of claim 1, wherein said first chip comprises one of a central-processing-unit (CPU) chip, a graphics-processing-unit (GPU) chip, a digital-signal-processing (DSP) chip, a flash memory chip, a dynamic-random-access-memory (DRAM) chip, a static-random-access-memory (SRAM) chip, a wireless local area network (WLAN) chip, a baseband chip, a logic chip, an analog chip, a power device, a regulator, a power management device, a global-positioning-system (GPS) chip, a Bluetooth chip, and a system-on chip (SOC) comprising one or more of a central-processing-unit (CPU) circuit block, a graphics-processing-unit (GPU) circuit block, a digital-signal-processing (DSP) circuit block, a memory circuit block, a baseband circuit block, a Bluetooth circuit block, a global-positioning-system (GPS) circuit block, a wireless local area network (WLAN) circuit block and a modem circuit block.

4. The system-in package of claim 1, wherein said thickness of said first semiconductor substrate is between 2 and 20 micrometers.

5. The system-in package of claim 1, wherein said second metal plug further contacts a second metal layer of said third chip, wherein said second metal layer is under said third semiconductor substrate.

6. The system-in package of claim 1 further comprising a third metal plug in said second chip, wherein said third metal plug passes through said second semiconductor substrate and contacts a second metal layer of said second chip, wherein said second metal layer is under a bottom surface of said second semiconductor substrate, wherein said first metal interconnect is further over said second chip and connected to said third metal plug.

7. The system-in package of claim 1, wherein said first metal plug passes through said first chip and contacts a contact point of said carrier.

8. The system-in package of claim 1 further comprising a third metal plug in said first chip, a fourth metal plug in said second chip, and a third metal interconnect in said first dielectric structure and over said first and second chips, wherein said third metal plug passes through said first semiconductor substrate and contacts a second metal layer of said first chip, wherein said second metal layer is under said bottom surface of said first semiconductor substrate, wherein said fourth metal plug passes through said second semiconductor substrate and contacts a third metal layer of said second chip, wherein said third metal layer is under a bottom surface of said second semiconductor substrate, wherein said third metal interconnect connects said third metal plug and said fourth metal plug.

9. The system-in package of claim 1, wherein said first chip has a different circuit design from a circuit design of said second chip.

10. The system-in package of claim 1 further comprising a dummy substrate over said carrier and in said gap, wherein said dummy substrate has a top surface substantially coplanar with said top surface of said first semiconductor substrate, wherein said first dielectric structure is further on said top surface of said dummy substrate.

11. The system-in package of claim 1 further comprising a metal bump connected to said second metal interconnect, wherein said metal bump comprises one of tin, copper, nickel, and gold.

12. The system-in package of claim 1, wherein said first metal interconnect comprises one of a signal trace, a power trace, and a ground trace.

13. The system-in package of claim 1, wherein said first insulating material comprises a sidewall dielectric layer on a sidewall of said first metal plug and on a top surface of said first metal layer, wherein said first metal plug is enclosed by said sidewall dielectric layer.

14. The system-in package of claim 1, wherein said second insulating material comprises an insulating ring in said third semiconductor substrate, wherein said second metal plug passes through and is enclosed by said insulating ring.

15. The system-in package of claim 1, wherein said second metal plug comprises an electroplated copper and a titanium-containing or tantalum-containing layer enclosing said electroplated copper.

16. The system-in package of claim 1, wherein said first metal interconnect comprises an electroplated copper layer and a titanium-containing or tantalum-containing layer at multiple sidewalls and a bottom of said electroplated copper layer, wherein said electroplated copper layer is in said first dielectric structure and over said first chip.

17. The system-in package of claim 1, wherein said first metal interconnect comprises an electroplated copper layer and a titanium-containing or tantalum-containing layer at a bottom of said electroplated copper layer but not at any sidewall of said electroplated copper layer, wherein said electroplated copper layer is in said first dielectric structure and over said first chip.

18. The system-in package of claim 1 further comprising a third metal plug in said third chip, wherein said third metal plug passes through said third semiconductor substrate and contacts a second metal layer of said third chip, wherein said second metal layer is under a bottom surface of said third semiconductor substrate, wherein said second metal interconnect is further connected to said third metal plug.

19. The system-in package of claim 18, wherein a total number of bit lines in parallel data communication between said first and third chips is more than 128, and one of said bit lines is provided by said first, second and third metal plugs and said first and second metal interconnects.

20. The system-in package of claim 1, wherein said first metal interconnect has a top surface substantially coplanar with a top surface of said first dielectric structure.